Intel Corporation

Krishna M Yellamilli

Gary N Hammond

Ken Shoemaker

Kin-Yip Liu

Anand B Pai

Wingcho Fung

A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Method for scheduling a flag generating instruction and a subsequent

A data latch/buffer cell for driving a data bus line conditionally precharges the line only during cycles prior those in which data is actually sampled. An input gate selectively enables a data input signal for application to a latching circuit. Prior to application of the data input, a conditional precharge signal is applied to the latch circuit to clear the previously latched data. A latch circuit is coupled to the gate of a pull-down transistor which drives the data bus. The conditional precharge signal is also coupled to the gate of a complementary pull-up transistor to precharge the bus line. Application of the conditional precharge signal to the gate of the pull-up transistor is delayed relative to turning off the pull-down transistor to preclude a rush through current in the driver.

Power reducing buffer/latch circuit

A data latching circuit includes a standard clock qualified transparent latch cell which receives an input data signal and an enable signal. The input data signal is also asserted at the input of a first transistor gate circuit which is controlled by the enable signal. The output of the transparent latch is asserted at the input of a second transistor gate circuit which is controlled by an inverted enable signal. The outputs of the two transistor gate circuits, only one of which is active at any time, are combined and buffered for output.

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San Jose, CA, United States of America

Krishna M Yellamilli