Micron Technology Incorporated

Intel Corporation

Intel Ndtm US LLC

Krishna Kumar Parat

Akira Goda

Pranav Kalavade

Haitao Liu

Khaled Hasnat

Shafqat Ahmed

Fatma Arzum Simsek-Ege

Sanh D Tang

Roger W Lindsay

Han Zhao

Shyam Sunder Raghunathan

Richard M Fastow

Neal R Mielke

Toru Tanzawa

Koji Sakui

Mark Alan Helm

Shigekazu Yamada

Prashant S Damle

Chandra V Mouli

Aaron S Yip

Andrew Bicksler

Yijie Zhao

Glen N Wada

Aurelio Giancarlo Mauri

Charan Srinivasan

Charles H Dennison

John David Hopkins

Kiran Pangal

Koichi Kawai

Timothy J Maloney

Shantanu R Rajwade

Guangyu Huang

Ian C Laboriante

Ramey M Abdelrahaman

Benben Li

Meng-Wei Kuo

Xin Sun

Srivardhan Gowda

Luan C Tran

Prashant Majhi

Yushi Hu

Gregory E Atwood

Alessandro Torsi

Srikant Jayanti

Carlo Musilli

Narayanan Ramanan

Tejas Krishnamohan

Kalpana Vakati

Gurtej S Sandhu

Tomoharu Tanaka

Nishant Sinha

Jeremy Binfet

Paul D Ruby

Giuseppina Puzzilli

Albert Fazio

Jie Sun

Rohit Sudhir Shenoy

Randy J Koval

Xuehong Yu

Iwen Chao

Hiroyuki Sanda

Daniel N Tang

Tyson M Stichka

Brian J Soderling

Wei Cao

Ali Khakifirooz

Durai Vishak Nirmal Ramaswamy

John K Zahurak

Thomas M Graettinger

Kerry Dean Tedrow

Ravi H Motwani

Aliasgar S Madraswala

Xin Guo

Nathan Franklin

Deepak Thimmegowda

Uday Chandrasekhar

Amol Ramesh Joshi

Owen W Jungroth

Yudong Kim

Kyu S Min

Shane J Trapp

Daniel Xu

Brian J Cleereman

Johnny Javanifard

Matthew Goldman

Rahul Agarwal

Purval Shyam Sule

Satoru Tamada

Jui-Yen Lin

Feng Zhu

Ervin T Hill

Chao Zhang

Stephen N Keeney

Liu Liu

Camila Jaramillo

Arash Hazeghi

Vijay Saradhi Mangu

Arun Thathachary

Henry Chao

An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.

3D NAND with inter-wordline airgap

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Apparatus and methods including source gates

Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

Weak erase pulse

An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.

Block-to-block isolation and deep contact using pillars in a memory array

An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Method and apparatus to mitigate hot electron read disturbs in 3D nand devices

Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.

Overcoming error correction coding mis-corrects in non-volatile memory

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

Multi-decks memory device including inter-deck switches

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

Memory cell pillar including source junction plug

An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

Apparatuses, systems, and methods for heating a memory device

Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices

Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed.

Flash memory components and methods

Growing community of inventors

Palo Alto, CA, United States of America

Krishna Kumar Parat