Intel Corporation

Krishna Kumar Ganesan

Tahir Ghani

Charles Henry Wallace

Leonard P Guler

Chanaka D Munasinghe

Vincent J Zimmer

Karunakara Kotary

Sudhakar Otturu

Mallik Bulusu

Elliot Tan

Sankaran M Menon

Mohit K Haran

Rolf H Kuehnis

Nicholas J Adams

Erik Lee Holt

Saurabh Morarka

Pronay Dutta

Nikhil Mehta

Sean Michael Pursel

Makram Abd El Qader

Sudhanshu John

Yasuharu Omi

Marie Conte

Eija Maarit Hillevi Manninen

Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.

Topside plugs for epitaxial contact formation

Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication

An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

Integrated circuit structures having cut metal gates with dielectric spacer fill

Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.

Techniques for monitoring errors and system performance using debug trace information

A computer boot apparatus and related method use a primary boot component (PBC) that is fixedly mounted in the computer. The PBC has a firmware element that is a non-volatile memory comprising a boot critical portion with instructions that initiate a boot of the computer. The PBC also has a policy manager and a version identifier. The PBC initializes the computer boot via the boot critical portion. The policy manager verifies and authenticates a secondary boot component that is removably attached to the computer.

Method and apparatus for hybrid firmware boot

In one embodiment, a system includes a display, a non-volatile memory to store one or more system software images, a processor to execute at least one of the one or more system software images, and a security engine to perform security applications. The security engine may include a first logic to receive a download package from a host computing system and store the download package in a first memory, authenticate the download package, and execute the download package to download and store a first system software image into the non-volatile memory. In addition, a second logic of the system may be configured to disable at least the display during the first system software image download and store. Other embodiments are described and claimed.

Performing power management during a download and execute operation

Technologies to enable, disable and control hardware subscription features. Computing devices communicate over a network to a subscription server to provide hardware platform information for each of the computing devices. As the subscription server receives hardware platform information, the subscription server determines the hardware features that are enabled, and further determines what hardware subscription options are available for each of the computing devices. When a hardware subscription option is selected/purchased by a computing device, subscription server provides a pre-boot update mechanism, such as a Unified Extensible Firmware Interface (UEFI) capsule, to act as a boot level program that enables hardware features on the computing device. Hardware subscription features are also securely protected using cryptographic engine modules.

Technologies for providing hardware subscription models using pre-boot update mechanism

Systems, apparatuses and methods may include technology that detects a migration request and conducts a first transfer, via a trusted execution environment (TEE), of storage context information from a first removable storage device to a secure memory region of a system in response to the data migration request. Additionally, the technology may conduct a second transfer, via the TEE, of the storage context information from the secure memory region to a second removable storage device, wherein the storage context information includes factory data, security data and boot firmware.

Automated secure data and firmware migration between removable storage devices that supports boot partitions and replay protected memory blocks

Technologies for updating firmware in a pre-boot environment include a mobile computing device having a firmware environment and an operating system. In the pre-boot environment, the mobile computing device extracts a firmware update from a capsule previously generated by the operating system and determines a power consumption setting for a hardware component as a function of the firmware update. The mobile computing device configures the hardware component based on the power consumption setting and applies the firmware update in response to configuring the hardware component. The firmware update may include a firmware driver executable in the firmware environment. The hardware component may include a peripheral device or a device controller of the mobile computing device. The mobile computing device may determine a power policy as a function of the firmware update, and determine the power consumption setting as a function of the power policy. Other embodiments are described and claimed.

Selective power management for pre-boot firmware updates

Technologies for managing the power usage of components of a computing device, while the components and the computing device are in a low-power state, such as a connected standby state. An embedded controller includes a wake-up timer designed to wake up the embedded controller during a low-power state to allow the embedded controller to perform its tasks. A power control system is configured to dynamically alter the timing cycle of the wake-up timer of the embodied controller based on operation data received. The dynamically altered timing cycle is designed to conserve power, but maintain functionality of the embedded controller.

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Hillsboro, OR, United States of America

Krishna Kumar Ganesan