Cadence Design Systems, Inc.

Krishna Chakravadhanula

Vivek Chickermane

Brian Edward Foutz

Christos Papameletis

Paul Alexander Cunningham

Steev Wilcox

Sameer Chakravarthy Chillarige

Dale Meehl

Sarthak Singhal

Puneet Kumar Arora

Patrick Gallagher

Rajesh Khurana

Prateek Kumar Rai

Steven Lee Gregor

Louis Christopher Milano

Subhasish Mukherjee

Sonam Kathpalia

David George Scott

Mehakpreet Kaur

Norman Robert Card

Brion L Keller

Anil Malik

Bharath Nandakumar

Ankit Bandejia

Nitin Parimi

Huafeng Yang

James S Allen

Dhruv Dua

Joe Swenton

A system includes a memory that stores instructions and a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a circuit layout module that generates an initial circuit layout in response to a circuit netlist. The circuit netlist includes functional logic, the test-point nodes interconnecting portions of the functional logic, and a plurality of test-point flops associated with scan-chains. The EDA application also includes a test-point flop allocation module that divides the test-point nodes into test-point sharing groups based on a physical location of the test-point nodes and based on a test-point allocation parameter. The module relocates each of the test-point flops proximal to a test-point sharing group to generate an adjusted circuit layout associated with the circuit design. The adjusted circuit layout is employable to fabricate an integrated circuit (IC) chip.

Physical awareness of test-point sharing in a circuit design

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

Clock-based test-point flop sharing in a circuit design

An integrated circuit (IC) chip includes an intellectual property (IP) core that executes logical operations to perform a function. The IC chip also includes a scan chain array for testing the IP core, and a pseudo random pattern generator (PRPG) that provides a pseudo random pattern based on a seed. The IC chip includes a spreader network that applies a first pseudo random code to a first edge of a die of the IC chip and a second pseudo random code to a second edge of the die of the IC chip in response to the pseudo random pattern and combines the first and second code to form a 2D code that is applied to the scan chain array. A security signature register of the IC chip outputs a signature corresponding to a response from the scan chain array that is employable to detect changes to an IC design.

IC chip with IC design modification detection

Embodiments included herein are directed towards a launch off shift circuit module. Embodiments included a first flip-flop configured to receive a clock signal and a scan enable signal. Embodiments may further include a combinational logic circuit configured to receive an input from the first flip-flop and a launch off shift mode signal. The first flip-flop and the combinational logic circuit may be located inside a launch off shift module boundary.

Launch off shift process

This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

Systems and methods for scan chain stitching

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

Test-point flop sharing with improved testability in a circuit design

Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at least one previously diagnosed electronic device, that the wherein the processor diagnoses defects in one or more of the plurality of electronic devices using the grouped failure data, and that the processor outputs the diagnosis results to the diagnosis results database.

System and method for multiple device diagnostics and failure grouping

Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time ('TAT'), test data volume, tester memory and cost associated with design for test ('DFT'), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

Method to improve testability using 2-dimensional exclusive or (XOR) grids

Systems and methods for creating learning-based personalized user interfaces for software applications are described. Exemplary embodiments provide for collecting usage data and applying machine learning techniques to identify and prioritize certain commands and options in the personalized user interface. The usage data can include Usage patterns, usage sequences, and the usage of certain commands and options in connection with, or following, certain other commands and options may also be identified, and the personalization-based prioritization can include, for example, the contents, position, and quantities of the commands and options within the interface.

Systems and methods for creating learning-based personalized user interfaces

Exemplary embodiments of the present disclosure relate to a clock distribution network for a scan design, which may include, for example, a clock signal network(s), and a plurality of partitioned clock signal networks coupled to the clock signal network(s) through a controlling logic(s); where the controlling logic(s) may be configured to stagger a clock signal from the clock signal network(s), and where each of the partitioned clock signal networks may be connected to a group of flip-flops. A first partitioned clock signal network of the partitioned clock signal networks may be connected to a first group of flip-flops and a second partitioned clock signal network of the partitioned clock signal networks may be connected to a second group of flip-flops, and where the first group of flip-flops may be different than the second group of flip-flops. The controlling logic(s) may include a shift register(s).

Low-power shift with clock staggering

Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Method for optimally connecting scan segments in two-dimensional compression chains

Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.

2D compression-based low power ATPG

A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.

Verification process for IJTAG based test pattern migration

Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.

SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores

An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.

Growing community of inventors

Vestal, NY, United States of America

Krishna Chakravadhanula