Intel Corporation

Microsoft Technology Licensing, LLC

Tahoe Research, Ltd.

Krishna Bharath

Adel A Elsherbini

Kaladhar Radhakrishnan

William J Lambert

Feras Eid

Aleksandar Aleksov

Johanna M Swan

Mathew J Manusharow

Shawna M Liff

Henning Braunisch

Yidnekachew S Mekonnen

Javier Soto Gonzalez

Beomseok Choi

Amruthavalli Pallavi Alur

Huong T Do

Zhichao Zhang

Suddhasattwa Nad

Michael J Hill

Meizi Jiao

Javier Soto

Omkar G Karhade

Kyu Oh Lee

Gerald S Pasdast

Yikang Deng

Nevin Altunyurt

Han Wui Then

Telesphor Kamgaing

Robert L Sankman

Georgios C Dogiamis

Kimin Jun

Mihir K Roy

Brandon M Rawlings

Jonathan P Douglas

Sriram Srinivasan

Dong Zhong

Christopher Schaef

Alexander Slepoy

Javier A Falcon

Mohammad Enamul Kabir

Srikrishnan Venkataraman

Haifa Hariri

Siddharth Kulasekaran

Hector A Aguirre Diaz

Stephen L Morein

Dmitri E Nikonov

Tanay Karnik

Kevin O'Brien

Zhiguo Qian

Brandon C Marin

Harish Krishnamurthy

Veronica Aleman Strong

Tarek A Ibrahim

Wei-Lun Kane Jen

Chong Zhang

Julien Sebot

Neelam Chandwani

Robert J Munoz

Kevin P O'brien

Nevine Nassif

Clive R Hendricks

Carleton L Molnar

Anne Augustine

Alexander Lyakhov

Nicolas Butzen

Sathya Narasimman Tiagaraj

Unnikrishnan Vadakkanmaru Veedu

Silvia Anali Soto De La Torre

Madhavi Tadepalli

Vivek Kumar Rajan

Timothy Francis Schmidt

Anuj Modi

Huong Do

Nathan Fritz

Fenghua Shen

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Embodiments disclosed herein include electronic packages with embedded inductors and methods of forming such electronic packages. In an embodiment, the electronic package comprises a package core, and a plated through hole (PTH) through a thickness of the package core. In an embodiment, the electronic package further and a magnetic shell around a perimeter of the PTH, where a height of the magnetic shell is less than the thickness of the package core. In an embodiment, the magnetic shell comprises a substantially vertical sidewall and a bottom surface that is tapered.

Stepped coax MIL PTHS for modulating inductance within a package

Technology is disclosed for a computing system with a printed circuit board having a top and bottom; an integrated circuit component coupled to the top of the board; a passive heat exchanger coupled to the top of the board and spaced from the integrated circuit component; at least one electronic component coupled to the printed circuit board below the top of the printed circuit board; and at least one heat pipe having an evaporator end adjacent the electronic component and extending away from the evaporator end along the bottom of the board to a condenser end above the top of the board, the condenser end being thermally coupled to the passive heat exchanger on the top of the board; wherein heat from electronic component is moved away from the electronic component and the integrated circuit component to the passive heat exchanger.

Computing system with cooling for controlling temperature of electronic components

A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.

Magnetic core inductors on package substrates

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Packaging architecture for disaggregated integrated voltage regulators

In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

Conformal power delivery structure for direct chip attach architectures

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

Magnetic core inductors in interposer

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

Direct bonding in microelectronic assemblies

Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

Package embedded magnetic power transformers for SMPS

An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Power delivery structures

Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Multi-phase switching regulators with hybrid inductors and per phase frequency control

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Microelectronic assemblies with inductors in direct bonding regions

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

High performance integrated RF passives using dual lithography process

Growing community of inventors

Chandler, AZ, United States of America

Krishna Bharath