International Business Machines Corporation

Kris V Srikrishnan

Manu J Tejwani

Rajiv V Joshi

John E Campbell

William T Devine

Dominic Joseph Schepis

James K Howard

James F White

Jer-Ming Yang

Stephen Edward Greco

Seshadri Subbanna

David R Hanson

Ananda H Kumar

Paul A Totta

Jin J Wu

Michael J Sullivan

Ronald Gene Walther

Paul S Ho

James R Lloyd

James M Oberschmidt

Alex A Behfar

Joseph J Gajda

Jasvir Singh Jaspal

Francis G Trudeau

Seshardi Subbanna

Manu J Tijwani

Sumit DasGupta

Hance H Huston, Iii

Devandra Gupta

David P Fouts

A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal semiconductor layer of an SOI substrate. A gate of the first FET overlies an upper surface of the common device layer, and a gate of the second FET underlies a lower surface of the common device layer remote from the upper surface. The first and second FETs share a common diffusion region disposed in the common device layer and are conductively interconnected by the common diffusion region. The common diffusion region is operable as at least one of a source region or a drain region of the first FET and is simultaneously operable as at least one of a source region or a drain region of the second FET.

Method and structure for buried circuits and devices

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

A method of forming multiple SOI wafers from a plurality of individual wafers each having a first side and a second side. The method includes forming an oxide surface on the first side on each of the plurality of individual wafers and forming a hydrogen rich region at a preselected depth on the second side on each of the plurality of individual wafers. The wafers are then bonded into a stacked configuration and heat treated to fracture the wafers at the hydrogen rich regions. This fracture forms at least two SOI wafers.

Simultaneous multiple silicon on insulator (SOI) wafer production

A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.

Process for restoring rejected wafers in line for reuse as new

A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1 Torr. Step coverage of the fill material and sputtering parameters are chosen to satisfy a predetermined relationship. The upper surface of the substrate comprises regions of exposed aluminum, aluminum-copper or copper alloys. After filling the vias and lines, the exposed aluminum, aluminum-copper or copper alloys are reacted with a gas containing germanium to form a germanium alloy over the upper surface of the substrate.

High aspect ratio low resistivity lines/vias by surface diffusion

A process applicable to the production of monocrystalline films improves on the Smart-Cut.RTM. process by using an etch stop layer in conjunction with the Smart-Cut.RTM. process. Because of the etch stop layer, no chemical-mechanical polishing (CMP) is required after fabrication. Thus, the thickness and smoothness of the device layer in the fabricated silicon on insulator (SOI) substrate is determined by the uniformity and smoothness of the deposited layers and wet etch selectivity, as opposed to the CMP parameters. Therefore, the smoothness and uniformity of the device layer are improved.

Smart-cut process for the production of thin semiconductor material films

A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6, can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

Method for fabricating high aspect ratio low resistivity lines/vias by

A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

A system and method for evaluating solder ball connections to a flip-chip or the like integrated circuit device through an extension of boundary scan testing circuits and techniques. The existence, size, and connective efficacy of solder balls deposited on pads are indirectly verified through the inclusion of a boundary scan driver and receiver with each pad. The respective drivers and receivers are connected to the complementing sections of a segmented pad metallurgy. The formation of a correct size solder ball connects the driver and receiver to allow boundary scan verification of all the electrical connections in the path. Thereby, low contact testing can be used to verify the integrity of the integrated circuit as well as any solder ball type die (chip) output contacts.

Complete chip I/O test through low contact testing using enhanced

A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

High aspect ratio low resistivity lines/vias with a tungsten-germanium

A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum allow form a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the-germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.

Antifuse element with electrical or optical programming

An electrically blowable fuse structure usable with organic insulators in microelectronic parts is provided. The fuse structure is made of a first heat resistant member, a fusing element and a second heat resistant member. The heat resistant members are in substantial contact with the fuse and thermally insulate the fuse from the organic insulator. The ends of each fuse are electrically connected to a pair conductors. A process for fabricating an electrically blowable fuse structure usable with an organic insulator is provided. A substrate with an organic insulator coating and containing electrically conductive features with exposed contacts is provided. A heat shield layer and a fuse layer are deposited sequentially and patterned by subtractive etching. Plurality of conductors are formed over so as to electrically connect each fuse element to a pair of conductors. A second heat resistant member is formed over the fuse area and the substrate is subsequently quoted with an organic insulator.

Electrically blowable fuse structure manufacturing for organic insulators

The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

Growing community of inventors

Wappingers Falls, NY, United States of America

Kris V Srikrishnan