Qualcomm Incorporated

Kris Tiri

Moinul H Khan

Bohuslav Rychlik

Mark Michael Schaffer

Jaya Prakash Subramaniam Ganasan

Feng Wang

Andrew Edmund Turner

George Patsilaras

Serag Gadelrab

Subbarao Palacharla

Anwar Q Rohillah

Joshua Stubbs

Vinod Chamarty

Simon Booth

Cristian Duroiu

Matthew Scott McGregor

Robert Nicholson Gibson

Yucong Tao

Jeong-Ho Woo

Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

Apparatus and method for detecting clock tampering

Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip ('SoC') are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate 'DDR' memory) from a closely coupled memory component (such as a low level cache &#x201c;LLC&#x201d; memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

System and method for managing bandwidth and power consumption through data filtering

Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Arbitrating bus transactions on a communications bus based on bus device health information and related power management

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San Diego, CA, United States of America

Kris Tiri