Imec Vzw

Katholieke Universiteit Leuven

Katholieke Universiteit Leuven, K.u. Leuven Research & Development

Kris Myny

Wim Dehaene

Jiwon Lee

Pierre Boulenc

Florian De Roose

Paul Heremans

Jan Genoe

Soeren Steudel

Vlatko Milosevski

Alexander Mityashin

Nikolaos Papadopoulos

Lynn Verschueren

Jonas Pelgrims

This patent disclosure relates to an ultrasound transducer including an array of ultrasound transducing elements, a plurality of transducer drive lines. The ultrasound transducer further includes an array of control circuits, wherein each individual control circuit includes a drive switch and a memory element, the drive switch comprising at least one thin-film transistor, the memory element being configured to store and control the state of the drive switch. The ultrasound transducer further configured so each individual ultrasound transducing element of the array of ultrasound transducing elements has one associated control circuit of the array of control circuits and one associated transducer drive line of the plurality of transducer drive lines, and wherein the ultrasound transducer is configured to, for each individual ultrasound transducing element, drive the individual ultrasound transducing element by the associated transducer drive line when the drive switch of the associated control circuit is in the on-state.

Ultrasound transducer and a system

An image sensor comprises at least two vertically stacked photo-sensitive devices wherein each respective photo-sensitive device comprises a stack of a top electrode, a first charge transport layer and an active layer. Each respective stack generates electrical charges in response to a corresponding predefined range of wavelengths of light incident on the image sensor. Each photo-sensitive device further comprises a second charge transport layer having a first portion, vertically aligned underneath the active layer, and a second portion, transfer region, protruding laterally to extend beyond the active layer. A dielectric layer separates the first portion from a bottom electrode providing a voltage for depleting the first portion, and the transfer region from a transfer gate providing a voltage for transferring the generated electrical charge to a floating electrical connection, shared by all stacked photo-sensitive devices. The floating electrical connection couples to a read-out-circuitry.

Image sensor comprising stacked photo-sensitive devices

A method of generating ultrasound by driving an array of ultrasonic transducers comprises a charge transfer procedure. The charge transfer procedure comprises switching a terminal of a first ultrasonic transducer of the array, at a first electric potential, to a charge distribution bus; switching a terminal of a second ultrasonic transducer of the array, at a second electric potential different than the first potential, to the charge distribution bus; and allowing charge to flow between the first ultrasonic transducer and the second ultrasonic transducer through the charge distribution bus.

Method of generating ultrasound and ultrasound generator

A photo-sensitive device comprises: an active layer configured to generate charges in response to incident light; a charge transport layer arranged below the active layer, wherein the charge transport layer comprises a first portion and a second portion being laterally displaced in relation to the first portion; a gate separated by a dielectric material from the charge transport layer, wherein said gate is arranged below the first portion and configured to control a potential thereof; and a transfer gate, which is separated by a dielectric material from a transfer portion of the charge transport layer between the first portion and the second portion, wherein the transfer gate is configured to control transfer of accumulated charges in the first portion to the second portion for read-out of detected light.

Photo-sensitive device and a method for light detection in a photo-sensitive device

Example embodiments relate to monolithically integrated antenna devices. One embodiment includes a monolithically integrated antenna device that includes a substrate having a first surface and a second surface. The monolithically integrated antenna device also includes a transistor component layer that includes at least one electronic component therein. Further, the monolithically integrated antenna device includes at least one antenna structure formed on the substrate or the transistor component layer. The antenna structure is configured to operate in a frequency range of between 30 kHz and 2.4 GHz. The substrate is configured to have a size that is the same or larger than the at least one antenna structure. The at least one antenna structure is formed in a stack with the transistor component layer and the substrate. The monolithically integrated antenna device is configured to shield the at least one electronic component in the transistor component layer from electromagnetic interference.

Monolithically integrated antenna devices

A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.

Active matrix display and method for driving an active matrix display

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

Growing community of inventors

Heusden-Zolder, Belgium

Kris Myny