Intel Corporation

Other

Kris G Konigsfeld

Andrew F Glew

Haitham H Akkary

Glenn J Hinton

Jeffrey M Abramson

Paul D Madland

David B Papworth

Jeffery M Abramson

Michael A Fetterman

Mandar S Joshi

Rohit A Vidwans

Brent E Lince

Scott Dion Rodgers

Michael W Rhodehamel

Robert W Martell

Keshavan K Tiruvallur

Mark A Timko

Milind A Karnik

Atiq A Bajwa

Joel C Huang

Warren R Morrow

William C Alexander, Iii

Atig A Bajwa

Prem Pahlajrai

James A Brayton

The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.

Method and apparatus for performing a store operation

The present invention provides a buffer management scheme for load operations that permits load operations to be stored for execution to memory. The buffer management scheme of the present invention maintains pointers identifies entries in the memory containing the oldest load operation and the next available location in the memory for a new load operation. By providing such management, the present invention allows memory operations and their execution by a device, such as a processor, to be coordinated with the operation of the system and other operations in the processor.

Apparatus for indicating an oldest non-retired load operation in an array

A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.

Method and apparatus for blocking execution of and storing load

A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

Method and apparatus for calculating effective memory addresses

The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.

Method and apparatus for performing multiple load operations to the same

A processor that performs integer-to-floating point transfers and vice versa using a store buffer in the processor to obviate the need for transferring data to memory and then back from memory. In this manner, these transfers may be performed to enable dedicated execution pipelines, such as integer execution pipelines and a floating point execution pipelines, to share data.

Method and apparatus for performing floating point to integer transfers

A method and apparatus disables and re-enables an interrupt during the execution of certain I/O and memory operations in an out-of-order processor. The out-of-order processor executes macroinstructions, wherein each macroinstruction comprises one or more microinstructions. The out-of-order processor comprises a fetch and issue unit and a reorder buffer that allows an interrupt to be serviced during the execution of the microinstructions making up any of a first class of macroinstructions. The reorder buffer, however, does not allow the interrupt to be serviced during execution of microinstructions making up a second class of macroinstructions. The second class of macroinstructions may include I/O and memory operations.

Method and apparatus for disabling interrupts in a highly pipelined

A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.

Out-of-order processor with a memory subsystem which handles

A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.

Computer system that maintains processor ordering consistency by

A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators. According to this embodiment of the microprocessor, the effective address of memory instructions can be reconstructed by utilizing the location designators of the ROB (Reorder Buffer) to find the corresponding storage location in the MOB (Memory Order Buffer) at which place the linear address for the instruction may be found. By associating both the retirement and exception information of the memory instructions stored within the storage locations of the re-order buffer with the corresponding memory instructions and information stored within the memory order buffer, the linear address of either the youngest, valid, retiring memory uop or the oldest, valid, excepted memory uop can be selected, written to memory and subsequently used to reconstruct the effective address of the memory instruction for use by an exception handler.

Method and apparatus for saving the effective address of floating point

A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

Method and apparatus for dispatching and executing a load operation to

A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.

Method and apparatus for handling code segment violations in a computer

The present invention provides a buffer management scheme for load operations that permits load operations to be stored for execution to memory. The buffer management scheme of the present invention calculates the readiness of multiple buffered load operations to speed up dispatch of at least one of the load operations to memory. By providing such management, the present invention allows memory operations and their execution by a device, such as a processor, to be coordinated with the operation of the system and other operations in the processor.

Method and apparatus for determining the dispatch readiness of buffered

A method and apparatus for dispatching load operations in a computer system. The present invention includes a method and apparatus for determining when the load operation is ready for dispatched to memory. The load operation is then scheduled to dispatch from memory and then dispatched to memory. In the present invention, a load is determined ready when it is no longer blocked, such that there is no condition which produces a resource or address dependency causing the load to be blocked.

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Portland, OR, United States of America

Kris G Konigsfeld