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Imec Vzw

Imec

Interuniversitair Microelektronica Centrum (imec)

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Interuniversitair Micro Elektronica

Kris A Baert

Sherif Sedky

Kazuhiro Kobayashi

Walter Gumbrecht

Matty Caymax

Paolo Fiorini

Jef Poortmans

Ann Witvrouw

Johan F Nijs

Chris Van Hoof

Vladimir Leonov

Cristina Rusu

Philippe Arquint

Filip Van Steenkiste

Carmen Bartic

Sonja Van Der Groen

A thermoelectric generator (TEG) and a method of fabricating the TEG are described. The TEG is designed so that parasitic thermal resistance of air and height of legs of thermocouples forming a thermopile can be varied and optimized independently. The TEG includes a micromachined thermopile sandwiched in between a hot and a cold plate and at least one spacer in between the thermopile and the hot and/or cold plate. The TEG fabrication includes fabricating the thermopiles, a rim, and the cold plate.

Method of manufacturing a thermoelectric generator and thermoelectric generator thus obtained

Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SiGelayer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Method for depositing polycrystalline SiGe suitable for micromachining and devices obtained thereof

The invention presents methods and systems for plating conductive patterns which at least result in a high uniformity and avoid parasitical plating effects. A plating system is disclosed for plating conductive patterns formed at a first surface of a substrate. The system is such that exposure surfaces not to be plated is inhibited. A first electrode of the system is immersed in the plating solution while the second electrode is in contact with another than the first surface of the substrate. The conductive patterns to be plated are temporarily electrically connected with the second electrode.

System and a method for plating of a conductive pattern

A device for detecting an analyte in a sample comprising an active layer comprising at least a dielectric material, a source electrode, a drain electrode and a semiconducting substrate which acts as current pathway between source and drain. The conductivity of said semiconducting layer can be influenced by the interaction of the active layer with the sample containing the analyte to detect. The device is fabricated such that properties like low price, disposability, reduced drift of the device and suitability for biomedical and pharmaceutical applications are obtained. To fulfill these requirements, the device described in this application will be based on organic-containing materials.

Device for detecting an analyte in a sample based on organic materials

A method of bonding a first substrate (10) to a second substrate (30) is described, comprising the steps of: coating an adhesive (28) onto a first major surface of said first substrate (10); aligning said first and second substrates (10, 30) so that said coated first major surface of said first substrate (10) is facing said second substrate (30) and is separated therefrom by a gap (47); deflecting at least one of said first and second substrates (10, 30) by exerting a pressure between said first and second substrates (10, 30) substantially at the center thereof so that the adhesive coating (28) substantially at the center of said first substrate (10) comes into contact with said second substrate (30); and allowing the remaining parts of said adhesive coated first major surface of said first substrate (10) to come into contact with said second substrate (30). Use of the method to produce composites, in particular transmissive liquid crystal display panels is also described.

Low temperature adhesion bonding method for composite substrates

A thin film transistor is produced by applying onto a non-silicon foundation, a thin film of silicon semiconductor material under such conditions that polycrystalline or microcrystalline material is formed. Source and/or drain regions of doped semiconductor material are then formed onto the film; following by applying insulating material onto the film, and a gate region onto the insulating material. The source and/or drain regions are applied so that such regions have a crystalline structure that depends upon the crystalline structure of the underlying thin film. The resulting source and drain regions have high lateral conductivity so that source and drain contacts can be made with reduced cross-sectional areas. The method may employ a self-alignment process to simplify device production.

Method of fabricating a thin film transistor

Growing community of inventors

Leuven, Belgium

Kris A Baert