International Business Machines Corporation

Western Digital Technologies, Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

Kraig Bottemiller

Brent William Jacobs

James Albert Pieterick

Richard Leo Galbraith

Weldon Mark Hanson

Travis Roger Oenning

Darin Edward Gerhart

Lee Anton Sendelbach

Cory Lappi

Adam Michael Espeseth

Fuminori Sai

William Jared Walker

Michael Joseph Ross

Michael J Anderson

Salvaging event trace information in power loss interruption (PLI) scenarios, for use in solid-state drive (SSD) and hard disk drive (HDD) storage devices. If volatile state information that is salvaged after an inadvertent power loss were to include event trace information, then such information can provide a valuable debug resource. Event trace information from volatile memory is copied to a second memory upon a power on which is in response to a PLI event. A corrupt state of context reconstruction data stored on non-volatile memory is detected, and an indication of the corrupt state is set. The event trace information is passed to the host if requested based on the indication.

Salvaging event trace information in power loss interruption scenarios

In some examples, a method includes determining, by a processor of a controller of a data storage device, that a voltage level of a capacitor in the data storage device is above a threshold voltage value, wherein the data storage device includes a capacitor circuit, and wherein the capacitor circuit includes the capacitor. The method further includes controlling, by the processor, the capacitor circuit to cause the capacitor to provide power to circuitry associated with memory devices of the data storage device along with power provided by a host device operably connected to the data storage device.

Residual capacitance performance booster

A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.

Apparatus and computer program product for implementing atomic data tracing

The invention includes apparatus and methods that allow a data storage device perform an enhanced data recovery procedure (DRP) that includes obtaining a new digital sampling of the voltages for the failing unit of data by re-reading the analog signal and converting it to digital form using an analog-to-digital conversion (ADC) using a fixed phase clock signal. The data samples are re-interpolated using a programmable delay line. The digital values representing the voltages are stored a buffer so that the data can be processed repeatedly using varying parameters as part of the data recovery procedure. Optionally the samples stored in the buffer can be processed in the reverse direction (from end of sector to beginning of sector) without requiring modification of the standard Viterbi detector since it inherently works on data processed in either direction.

Data storage device with data recovery process using fixed phase clocking for analog-to-digital conversion

Method, apparatus and computer program product for implementing atomic data tracing

A method and profiling cache for management of virtual memory includes a set of entries stored in the profiling cache. Each entry of the set of entries includes a page address, a time stamp for the page address and a least recently used (LRU) count; and the LRU count is updated for each access of the page address. Entries in the profiling cache are cast out using the LRU counts. A translation lookaside buffer (TLB) includes a first TLB section for storing a plurality of temporarily pinned entries and a second TLB section for storing a plurality of non-pinned entries. Responsive to a TLB interrupt, an entry is loaded in the second TLB section using a first in first out algorithm for replacing the non-pinned entries. The first TLB portion is periodically updated utilizing identified ones of the set of entries in the profiling cache having oldest time stamps.

Method and profiling cache for management of virtual memory

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Rochester, MN, United States of America

Kraig Bottemiller