Hitachi Displays, Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Japan Display Inc.

Kozo Yasuda

Katsumi Matsumoto

Toshio Miyazawa

Hiroshi Kageyama

Atsushi Hasegawa

Terunori Saitou

Takeshi Yonekura

Hideo Sato

Takuo Kaitoh

Yasukazu Kimura

Toshihiko Itoga

Hideki Nakagawa

Naohisa Ando

A photosensor array includes plural photosensor pixels. Each of the photosensor pixels includes a lower electrode, an amorphous silicon film, an n-type amorphous silicon film, and an upper electrode. The photosensor array includes plural scanning lines connected to the upper electrodes, plural read lines connected to the lower electrodes, a scanning circuit that is connected to the plural scanning lines, and sequentially supplies a selection scanning signal of a first voltage to the respective scanning lines, a first unit that inputs a second voltage higher than the first voltage to the plural read lines in a blanking period of one horizontal scanning period, and thereafter puts the plural read lines into the floating state, and a second unit that outputs a voltage change in each of the read lines within one horizontal scanning period as the sensor output voltage of the photosensor pixel.

Photosensor having upper and lower electrodes with amorphous silicon film and n-type amorphous silicon film therebetween and photosensor array

A photosensor includes a lower electrode formed of a metal film, an amorphous silicon film disposed on the lower electrode, an n-type amorphous silicon film disposed on the amorphous silicon film, an upper electrode that is disposed on the n-type amorphous silicon film, and receives a first reference voltage, a capacitive element connected between the lower electrode and a second reference voltage, a switch circuit that inputs a first supply voltage to the lower electrode in an on-state, and puts the lower electrode into a floating state in an off-state, and a detector circuit that detects a voltage change in the lower electrode after irradiating the amorphous silicon film for a given period with light when the switch circuit is on.

Photosensor and photosensor array with capacitive element

The present invention provides a photosensor device including: a photodiode array in which photodiodes are arranged in an array shape; scanning lines which are coupled to first electrodes of the photodiodes in respective lines of the photodiode array; read lines which are coupled to second electrodes of the photodiodes in respective columns of the photodiode array; a scanning circuit which is coupled to the scanning lines and sequentially supplies a selected scanning signal to the respective scanning lines in each horizontal scanning period; and a signal processing circuit which is coupled to the read lines and loads each voltage fluctuation of the read lines in one horizontal scanning period as signal voltage when reading a signal, wherein each of the photodiodes is made of amorphous silicon or microcrystal silicon, and forward bias voltage is applied to each of the photodiodes when reading a signal.

Photosensor device

Each optical sensor element includes an upper electrode, a lower electrode, and a light dependent variable resistance element formed of amorphous silicon. Each optical sensor pixel includes: a capacitive element between the lower electrode and a reference voltage line; a first transistor inputting a first power source voltage to a second electrode, connecting a first electrode to the lower electrode, and inputting a second clock to a control electrode; a second transistor inputting a second power source voltage to a second electrode, and connecting a control electrode to the lower electrode; and a third transistor connecting a second electrode to a first electrode of the second transistor, connecting a first electrode to the output line, and inputting a first clock to a control electrode.

Optical sensor circuit or array including optical sensor element having a light dependent variable resistance element

The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.

Display device

A display device includes a memory unit formed in each pixel to store video data and including a first inverter circuit whose input terminal is connected to a first node and whose output terminal is connected to a second node and a second inverter circuit whose input terminal is connected to the second node and whose output terminal is connected to the first node, a first transistor connected between the output terminal of the second inverter circuit and the video line, and a second transistor connected between the first node and the video line, in which at the time of reading the video data, the first transistor is turned ON, and the second transistor is turned OFF, to output the video data stored in the memory unit to the video line.

The number of wirings between a scanning circuit and a plurality of scanning lines is decreased with a more simple circuit configuration than a conventional one. The scanning lines are grouped into kN&#xd7; . . . &#xd7;k2 groups. First to Nth groups of gate wirings are included, each of the first to Nth groups being composed of kn (1&#x2266;n&#x2266;N) gate wirings. A scanning line drive circuit outputs a first selection scanning voltage which selects the scanning lines in each of the groups every horizontal scanning period to the first group of k1 gate wirings, outputs a second selection scanning voltage which selects the scanning lines in one of groups in a second stage where k2 groups constitute one unit every k1 horizontal scanning periods to the second group of k2 gate wirings, and outputs an mth selection scanning voltage which selects the scanning lines in one of groups in an mth stage where k (m&#x2212;1) groups in a (m&#x2212;1)th stage constitute one unit every (k (m&#x2212;1)&#xd7; . . . &#xd7;k1) horizontal scanning periods to an mth group of km gate wirings.

Provided is a display device including a level shift circuit, which includes a thin film transistor having a polycrystalline semiconductor layer, and which realizes a reliable operation even when a threshold of the thin film transistor varies. The display device includes: a board; and the level shift circuit which includes the thin film transistor having the polycrystalline semiconductor layer, and is formed on the board, in which the level shift circuit includes: a plurality of source-input level shift circuits including a plurality of unit level shift circuits having drain resistors different in value from one another; and a selection circuit, which selects one of outputs from the plurality of unit level shift circuits as an output from a normally operated unit level shift circuit.

A display device includes a display panel having (m&#xd7;n) pieces of pixels wherein m and n are integers of 2 or more, n pieces of video lines, and m pieces of scanning lines, a video line address circuit, a scanning line address circuit, n pieces of video line vector circuits which are connected to the respective output terminals of the video line address circuit and input the same video data to the pixels at address positions from a starting address to an ending address at one time, and m pieces of scanning line vector circuits which are connected to the respective output terminals of the scanning line address circuits and input the selective scanning voltages to the pixels at the address positions from the starting address to the ending address at one time.

An object of the present invention is to increase the speed of the level shifting operation in a display device having a level shift circuit formed of polysilicon thin film transistors. The present invention provides a display device having a level shift circuit wherein the above described level shift circuit has: a thin film transistor having a semiconductor layer formed of a polysilicon layer; a load resistance element connected between a second electrode of the above described thin film transistor and a reference power supply; and a waveform rectifying circuit connected to the second electrode of the above described thin film transistor, and a diode element of which the anode region is connected to the first electrode of the above described thin film transistor and of which the cathode region is connected to the second electrode of the above described thin film transistor.

The present invention is to prevent a capture error of display data caused by a delay due to a built-in driving circuit in a display device with a built-in driving circuit. The display device comprises: a display area having a plurality of sub pixels; and a driving circuit formed at the periphery of the display area; wherein the driving circuit includes: a first scanning circuit that performs scanning in a first direction; and a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit; wherein the driving circuit includes a timing correction circuit which corrects the timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external; wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; and wherein a transmission line up to the latch circuit of the display data and a transmission line up to the timing correction circuit of the display data synchronization clock are adjacently arranged.

In the display device which is used in a miniaturized portable equipment, when a drive circuit is also connected on the same substrate as pixels, an input signal of low voltage has a level thereof shifted even when the threshold value is large or fluctuated. The display device includes pixel electrodes, switching elements which supply video signals to the pixel electrodes, and a drive circuit which supplies the video signals to the switching elements on the same substrate, wherein the drive circuit includes a level shift circuit, the level shift circuit includes a transistor. In a state that the transistor assumes an ON state, when an input signal is inputted to a source terminal and the input signal is at a low voltage level, a drain terminal assumes a low voltage level. Further, even when the input signal is at a high voltage level equal to or lower than a threshold value, the drain terminal outputs a voltage equal to or more than the threshold value as a high level voltage.

A display device which is used in a miniaturized portable information device can exhibit the low power consumption even when a display is not changed over for a long period in a state that a battery or the like is used as a power source. The display device can maintain a high numerical aperture by suppressing the number of parts even when a memory element is provided to a pixel. In a liquid crystal display device, a pixel exhibits the low power consumption by including a memory element and thus preventing the transmission of a video signal. By making use of a charge held in a pixel electrode of a liquid crystal display panel, a signal for AC driving is formed in the inside of a pixel thus performing AC driving to perform a display without deteriorating liquid crystal even when the video signal is not rewritten. The liquid crystal display device can realize the memory element with the simple constitution without sacrificing a numeral aperture.

Low power display device

A display device which arranges a memory part for every display pixel is configured to prevent a charge from remaining in liquid crystal when a power source is turned off. Each display pixel includes a memory part for storing video data, a pixel electrode, and a switch part for selectively applying a first video voltage or a second video voltage different from the first video voltage to the pixel electrode corresponding to the video data stored in the memory part. The display device further includes a reset circuit for allowing the first video voltage and the second video voltage to have the same voltage when a power source of the display device is turned off.

An oscillator circuit includes (2n+1) inverters connected in series when n is a natural number, an integrator circuit having an input terminal connected to an output terminal of a (2n+1)-th inverter and an output terminal connected to an input terminal of a first inverter, first and second p-type transistors connected in series between the input terminal of the first inverter and a first reference potential, and first and second n-type transistors connected in series between the input terminal of the first inverter and a second reference potential. An output voltage of a j-th inverter is applied to control electrodes of the first p-type transistor and the first n-type transistor. An output voltage of a k-th inverter is applied to control-electrodes of the second p-type transistor and the second n-type transistor. Symbol j is an odd number, k is an even number, and j&#x3c;k=2n is satisfied.

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Mobara, Japan

Kozo Yasuda