Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Other

Elpida Memory, Inc.

Kozo Watanabe

Kenichi Kuroda

Hirohiko Yamamoto

Masayuki Kojima

Atsushi Ogishima

Shuji Ikeda

Norio Suzuki

Norio Ishitsuka

Yasuko Yoshida

Kiyonori Ohyu

Hiroyuki Uchiyama

Yoshiyuki Kaneko

Masahiro Moniwa

Hiroyuki Miyazawa

Kyoichiro Asayama

Masaki Nagao

Atushi Ogishima

Syunichi Hashimoto

Naokatsu Suwanai

Nozomu Matsuda

Hiroki Soeda

Kazuya Endo

Takashi Yoneoka

Takashi Aoyama

Keiji Okamoto

Akira Takamatsu

Shinichi Horibe

Maki Shimoda

Fukuo Owada

Hiroyuki Ichizoe

Masaaki Shinohara

Hideo Miura

Takashi Hashimoto

Hideki Miyazaki

Kenichi Onda

Shoji Yoshida

Yasuo Matsuda

Masashi Sahara

Kunihiko Kato

Masatoshi Taya

Shigeya Toyokawa

Kenji Kanamitsu

Shinichi Tanabe

Akihiko Kanouda

Kazuyoshi Oshima

Kousuke Okuyama

Osamu Tsuchiya

Yoshifumi Kawamoto

Atsushi Hiraiwa

Takashi Nishida

Hideki Aono

Akihoko Kanouda

A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.

Semiconductor device and a method of manufacturing the same and designing the same

There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DPof relatively wider area and the second dummy pattern DPof relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DPoccupy a relatively wide region among the dummy region FA.

Method of manufacturing a semiconductor device including dummy regions and dummy wirings

To reduce size of a finished product by reducing the number of externally embedded parts, embedding of a Schottky barrier diode relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. It is general practice to densely arrange a number of contact electrodes in a matrix over a Schottky junction region. A sputter etching process to the surface of a silicide layer at the bottom of each contact hole is performed before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.

Semiconductor integrated circuit device and a method of manufacturing the same

Semiconductor device having active region and dummy wirings

To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.

Method of manufacturing a semiconductor device having an active region and dummy patterns

A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and ntype semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSilayer is formed over the ntype semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSilayer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.

Semiconductor device and a method of manufacturing the same

A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor. The sidewall spacers of the first field effect transistor include a first silicon oxide film, a first silicon nitride film over the first silicon oxide film and a second silicon oxide film over the first silicon nitride film.

Semiconductor device with rewritable nonvolatile memory cell

A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

Growing community of inventors

Kokubunji, Japan

Kozo Watanabe