Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Matsushita Electric Co. Ind, Ltd.

Kozo Kimura

Tokuzo Kiyohara

Hideshi Nishida

Tetsuya Tanaka

Hiroshi Kadota

Nobuo Higaki

Kunihiko Hayashi

Makoto Hirai

Kazuya Furukawa

Kazushi Kurata

Shigeki Fujii

Toshio Sugimura

Kosuke Yoshioka

Hiroyuki Morishita

Takeshi Furuta

Satoshi Takashima

Hiroshi Mizuno

Hideyuki Ohgose

Junji Michiyama

Tomohiko Kitamura

Toshiaki Tsuji

Ryoji Yamaguchi

Ryuji Matsuura

Hiroaki Hirata

Manabu Kuroda

Akifumi Yamana

Nobuhiko Yamada

Takeshi Tanaka

Satoshi Yamaguchi

Yutaka Tanaka

Yoshiyuki Wada

Akira Miyoshi

Takahiro Watanabe

Toshimichi Matsuzaki

Toshiyuki Ochiai

Yuya Shigenobu

Hiroyuki Oka

Atsushi Ito

Yosuke Furukawa

Kousuke Yoshioka

Kosuki Yoshioka

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one of compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

Integrated circuit with multipurpose processing and for video/audio processing optimization

An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

Integrated circuit for video/audio processing

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

Information processing apparatus and exception control circuit

An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

A variable length code decoding apparatus according to the present invention includes: an extracting unit which extracts a bit string from a beginning of a bit stream; a first storage unit for storing a plurality of code words in which one piece of data has been coded, and decoded data and code lengths respectively corresponding to the code words; a second storage unit for storing a plurality of code words in which two or more pieces of data have been coded, and decoded data and code lengths respectively corresponding to the code words; a first judging unit which judges whether one of the code words stored in the first storage unit is included in the extracted bit string, and, when judged as being included, outputs the decoded data and the code length of the code word; and a second judging unit which judges whether a code word stored in the second storage unit is included in the extracted bit string, and when judged as being included, outputs the decoded data and the code length of the code word, wherein the extracting unit extracts the bit string to be decoded next in the same cycle as a cycle in which the judgment was made by the first judging unit, and extracts the bit string to be decoded next in a cycle following the cycle in which the judgment was made by the second judging unit.

Variable length code decoding apparatus and method with variation in timing of extracting bit string to be decoded depending on code word

The parallel execution processorfetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unitassigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unitforms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor

Parallel execution processor and instruction assigning making use of group number in processing elements

A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Data processor and program for processing a data matrix

A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

Media processing apparatus which operates at high efficiency

A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

Microprocessor

Growing community of inventors

Toyonaka, Japan

Kozo Kimura