Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Other

Kabushiki Kaisha Kumagaigumi

Kozo Katayama

Yoshiaki Kamigaki

Shinichi Minami

Toshihiro Tanaka

Yutaka Shinagawa

Mitsuru Hiraki

Nozomu Matsuzaki

Masamichi Fujito

Takashi Yamaki

Kazufumi Suzukawa

Hiroyuki Tanikawa

Yukiko Umemoto

Masataka Kato

Takanori Yamazoe

Shiroo Kamohara

Takashi Hashimoto

Tatsuya Kunikiyo

Yoshiyuki Kawashima

Yasushi Ishii

Daisuke Okada

Toshikazu Matsui

Eiji Tsukuda

Kentaro Saito

Koichi Toba

Kenichiro Sonoda

Sigeo Ihara

Satoru Machida

Dai Hisamoto

Nobutaka Nagasaki

Takeo Kanai

Toru Toyabe

Shuichi Yamamoto

Naohiro Hosoda

Hajime Akimoto

Nobuhiro Oodaira

Hiroshi Yoshigi

Junji Shigeta

Shigekazu Horiya

Takayoshi Yokota

Takashi Tase

Hiroshi Watase

Eiji Yamasaki

Masatoshi Takahashi

Sadao Uno

Daijiro Tanabe

A semiconductor device includes a plurality of nonvolatile memory cells (). Each of the nonvolatile memory cells comprises a MOS type first transistor section () used for information storage, and a MOS type second transistor section () which selects the first transistor section. The second transistor section has a bit line electrode () connected to a bit line, and a control gate electrode () connected to a control gate control line. The first transistor section has a source line electrode () connected to a source line, a memory gate electrode () connected to a memory gate control line, and a charge storage region () disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc&#x3c;tm.

Semiconductor device

A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.

Semiconductor device and manufacturing method of semiconductor device

To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Manufacturing method of semiconductor device

A semiconductor processing device according to the invention includes a first non-volatile memory () for erasing stored information on a first data length unit, a second non-volatile memory () for erasing stored information on a second data length unit, and a central processing unit (), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

Semiconductor processing device and IC card

A p-type well region is formed at a main surface of a semiconductor substrate. An n-type impurity region is located under the p-type well region. A first insulating layer is formed on the main surface of the semiconductor substrate and on the p-type well region. A charge-storage insulating layer is formed on the first insulating layer. A gate electrode layer is formed on the charge-storage insulating layer. An erase operation is performed by applying a forward bias to the p-type well region and the n-type impurity region to generate hot carriers and inject the hot carriers into the charge-storage insulating layer.

Nonvolatile semiconductor memory device and operation method thereof

In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrodeof the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrodeare formed in a multilayer structure including an electrode material filmA and an electrode material layerB, and the gate electrodeis a single layer structure formed at the same time as the electrode material filmA of the control gate.

Semiconductor device and a method of manufacturing the same

Growing community of inventors

Tokyo, Japan

Kozo Katayama