Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Kozaburo Kurita

Masahiro Iwamura

Kazuo Kato

Hideo Maejima

Takashi Hotta

Yasuhiro Nakatsuka

Shigeya Tanaka

Tadaaki Bandoh

Sin-ichi Sinoda

Yoji Nishio

Fumio Murabayashi

Tetsuo Nakano

Shoichi Kotoku

Ikuro Masuda

Masahiro Ueno

Takashi Sase

Masatoshi Hasegawa

Yuji Yokoyama

Shuichi Miyaoka

Hiroshi Akasaki

Hideki Sakakibara

Akihiko Kanouda

Nobuaki Miyakawa

Hirokazu Aoki

Mitsugu Kusunoki

Yuko Ito

Atsuo Hotta

Yosuke Kawakubo

Ryusuke Sahara

Koki Tsutsumida

Tomoji Nakamura

Atsushi Hazeyama

Yasuyoshi Sunaga

Yuuji Suzuki

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S) and a predetermined linearity condition (S).

Semiconductor integrated circuit

A semiconductor apparatus including built-in power supply circuits capable of supplying a large current with high voltage accuracy. The semiconductor apparatus includes a semiconductor chip including a circuit area and power supply circuits, coils and capacitors. The semiconductor chip, coils and capacitors are provided in a package. Each power supply circuit, a coil and a capacitor compose a switching regulator. The semiconductor chip and the package are connected such that a power supply voltage which will be produced by the switching regulator is supplied to the circuit area. The power supply circuit is supplied with a power supply voltage from the outside of the semiconductor apparatus.

Semiconductor apparatus comprising a semiconductor chip with a power supply circuit and a smoothing circuit disposed outside the semiconductor chip

An over-current detection circuit using the ON-voltage of a main MOSFET is provided, which is resistant to process variations of a main MOSFET and is not easily influenced by switching noise. Separately from a main MOSFET (Q), a sense MOSFET (Q) whose size is 1/m of the main MOSFET is provided and it is caused to be normally on. A DC ON-voltage generated when a current that is 1/m of an over-current value is caused to flow through the sense MOSFET is obtained as a reference voltage for over-current setting. The ON-voltage when the main MOSFET is on is sampled and held, and it is obtained as a DC voltage. These DC voltages are compared in a comparator (COMP).

Over-current detection circuit and method for power-supply device

In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

Semiconductor integrated circuit having programmable delays for generating timing signals with time difference being non-integral multiple of clock cycle

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

Semiconductor integrated circuit device

A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

Phase-locked loop circuit, information processing apparatus, and information processing system

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K , And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K .

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.

System including phase lock loop circuit

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Information processor and information processing system utilizing clock

A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal. This current signal is combined with the current signal from the compensation circuit to control the oscillation frequency of a ring oscillator comprising a current-controlled delay circuit the same in structure as the above current-controlled delay circuit. On the basis of the oscillation signal from the ring oscillator, the second frequency signal and clock signals needed in the semiconductor integrated circuit are generated.

Clock pulse generator

A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.

Semiconductor integrated circuit device having bipolar transistor and

Data processing system generating clock signal from an input clock,

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Hitachi, Japan

Kozaburo Kurita