Winbond Electronics Corporation

Windbond Electronics Corp.

Koying Huang

Johnny Chan

Teng Su

Chi-Shun Lin

Nir Tasher

Valery Teper

Ngatik Cheung

Douk-Hyoun Ryu

Seow-Fong Lim

Dennis Chin Cheng

A memory device includes a controller configured for initiating a program operation for a first column of memory cells which belongs to a group of memory cells; setting a verify condition which comprises a leakage current threshold during a leakage current verifying operation; performing, via a leakage current verifying circuit, a leakage current verifying operation for the first column of the memory cells by applying a negative voltage sweep to each of first remaining M−1 unselected WLs of the M WLs until finding a first negative voltage resulting in the first column of the memory cells having passed leakage current threshold; and applying the program operation for the first column of the memory cells by applying the first negative voltage to each of the first remaining M−1 unselected WLs of the M WLs and a positive bit line voltage for the N BLs.

Memory device with leakage current verifying circuit for minimizing leakage current

A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.

Writing method of flash memory and memory storage device

A non-volatile memory device and a non-volatile memory erasing operation method is provided. The method includes the following. A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells of the non-volatile memory through a first erasing pulse. A first verification operation is performed to confirm whether the threshold voltage of each of the memory cells is less than an erasing target voltage level. In response to at least one of the memory cells failing the first verification operation, a second erasing operation is performed. The second erasing operation includes selecting the at least one memory cell failing the first verification operation, and reducing the threshold voltage of the at least one memory cell to be less than the erasing target voltage level through a second erasing pulse.

Non-volatile memory device and erasing operation method thereof

In an aspect, the memory device includes not limited to a memory array, a leakage current verifying circuit, and a controller. The controller is configured to perform an erase operation for a first column of memory cells connected to a first WL, set a verify condition including a leakage current threshold, perform a leakage current verifying operation for the first column of the memory cells by comparing a leakage current of a cell of the first column of the memory cells to the leakage current threshold, detect a failure of the first column in response to a cell having the leakage current being above the leakage current threshold, and perform a post-program operation to repair the failure of the first column of the memory cells.

A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.

NOR flash memory apparatus and recover and read method thereof

The disclosure is directed to a method and an apparatus for verifying an operation performed by a cell of a RRAM. In an aspect of the disclosure, the method of verifying an operation performed by a cell of a RRAM would include not limited to performing a first write operation by applying a first write voltage on a cell of the RRAM; measuring a first resistance and a first rate of change of the resistance of the cell; detecting whether the first rate of change of the resistance is below a negative change of resistance threshold; detecting whether the first resistance is below a target resistance value in response to having detected that the first rate of change of the resistance is below the negative change of resistance threshold; and having determined the cell is valid in response to having detected the first resistance dropping below the target resistance value.

Method and electronic circuit for verifying operation performed by cell of RRAM

A non-volatile memory device and a method thereof that are capable of improving programming speed are introduced. The non-volatile memory device includes a memory array, a charge-pump circuit, a bias detection circuit and a memory controller is introduced. The memory array includes a plurality of memory cells; and a charge-pump circuit is configured to generate a charge-pump voltage. The bias detection circuit is coupled to the charge-pump circuit and is configured to determine whether a level of the charge-pump voltage is less than a first pre-determined threshold value. The memory controller is coupled to the bias detection circuit and is configured to pause a programming operation being performed on at least one of the plurality of memory cells when the bias detection circuit determines that the level of the charge-pump voltage is less than the first pre-determined threshold value.

Non-volatile memory device and method capable of pausing and resuming programming operation

A resistive random access memory device which includes a resistive random access memory array, a sense amplifier and a boosting circuit. The sense amplifier is coupled to the resistive random access memory array and is configured to sense a resistance value of the memory cell. The boosting circuit is coupled to the memory cell of the resistive random access memory array and is configured to boost a reset voltage in a boosting period of a reset period according to the resistance value of the memory cell. The boosting period is from beginning of the reset period, and the memory cell is biased with the reset voltage in the reset period to perform the reset operation. A method for a reset operation on a resistive random access memory device is also introduced.

Resistive random access memory device and method for performing memory operations

The disclosure is directed to a power drop reset circuit which includes not limited to: a first step circuit configured to detect a change of a power supply voltage per unit of time and transmit an enable signal in response to the first step circuit having determined that the change of the power supply voltage per unit of time has dropped below zero, wherein the first step circuit does not consume any current when the Vcc change per unit of time is greater than or equal to zero; and a second step circuit electrically connected to the first step circuit and configured to detect the Vcc in response to having received the enable signal and generate a power drop reset signal in response to having determined that the Vcc has dropped below a predetermined operating voltage, wherein the second step circuit consumes an operating current after receiving the enable signal.

Power drop reset circuit for power supply chip and power drop reset signal generating method

A method for detecting a flash memory array includes a plurality of word lines, a plurality of bit lines, and a source line, includes executing a first detection process. The first detection process includes: applying a first positive voltage to a P-type well of the flash memory array; applying a ground to all the word lines; floating the bit lines and the source line; determining whether a leakage current flowing through the P-type well exceeds a leakage threshold; and when the leakage current exceeds the leakage threshold, determining that at least one of the word lines is short-circuited with at least one of the bit lines or the source line.

Detection methods for NOR flash memory

This invention introduces a resistive random access memory (RRAM) device, a write verify method and a reverse write verify thereof which are capable of improving the performance of RRAM operations and improving the uniform performance for each RRAM cell. A first resistance value sensed from a RRAM cell is compared with a plurality of reference resistance values to obtain a comparison value. A set or a reset operation is performed on the RRAM cell by applying a first set or reset pulse to change the first resistance value to a second resistance value. Next, the second resistance value is compared with the comparison value to determine whether to continue the set or reset operation on the RRAM cell.

Resistive random access memory (RRAM) device, write verify method and reverse write verify method thereof

A memory device and a data reading method are provided. A dummy circuit performs a read operation in synchronism with a data access circuit according to an address signal, so as to estimate time points at which the data access circuit completes each of operating procedures, and enable the data access circuit to execute a next operating procedure when completing an operating procedure.

Memory device and data reading method thereof

A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.

Apparatus for providing adjustable reference voltage for sensing read-out data for memory

In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of Vvalues without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high Vvalues, and lower frequency for low Vvalues.

Apparatus and method for read time control in ECC-enabled flash memory

A resistive random-access memory device includes a RRAM array including a plurality of RRAM cells coupled to a source line, a controller, a bit-line decoder, and a sense circuit. Each of the RRAM cells storing a logic state and is selected by the corresponding bit line and word line. The controller selects a selected RRAM cell by a bit-line signal and a selected word line and determines the logic state according to a sense signal. The bit-line decoder couples a data bit line to the selected bit line according to a bit-line signal. The sense circuit is coupled to the data bit line and compares a memory current flowing through the selected RRAM with a reference current to generate the sense signal. The sense circuit sinks the memory current from the data bit line when operating in a reset operation and a reverse read operation.

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San Jose, CA, United States of America

Koying Huang