Fujitsu Corporation

Koutarou Tagawa

Toshiaki Saruwatari

Toru Okabayashi

Kouj Arai

The invention is the microcontroller, which comprises CPU, a bus controller, an instruction address bus of a first bit number and an instruction code bus of a second bit number, which connect between the CPU and bus controller, and, further, a debug support unit, which is connected to the instruction address bus and instruction code bus. This debug support unit is also connected to an external in-circuit emulator via a tool bus of a third bit number that is smaller than the first bit number and via a bus-status signal line that reports on the status of this tool bus. The debug support unit has a data output circuit, which, in response to the status information signal, when the branch information contains a branch, outputs the converted instruction address serially to the tool bus, and when the branch information contains no branch, outputs a branchless signal to the tool bus.

Microcontroller with debug support unit

In the microcomputer, the debug target circuit and the debugging circuit with an interface module to the in-circuit emulator are independently supplied with drive powers. Drive power is supplied to the debug target circuit and the debugging circuit, and various debug information is set by the in-circuit emulator. Thereafter, only supply of drive power to the debug target circuit is stopped. While the various debug information is held at the debugging circuit, supply of drive power to the debug target circuit is restarted. The debugging just after power throw-in is performed based on the debug information held in the debugging circuit.

Microcomputer with debug supporting function

A semiconductor integrated circuit including a debugging support unit and a buffer memory for temporarily storing trace data, the debugging support unit comprising a break detection member that detects a break signal externally inputted and a break determining member that determines whether the break signal requests to shift to break processing after outputting all the trace data stored in the buffer memory or the break signal requests to shift to the break processing with immediately suspending trace data outputting.

Break determining circuit for a debugging support unit in a semiconductor integrated circuit

A conflict detection unit monitors an input of branch information and an input of data access information. When an output data selection unit receives a notification from the conflict detection unit that there has arisen the conflict between the input of the branch information and the input of the data access information, the output data selection unit outputs branch information, and then data access information delayed by a delay unit, thereby outputting trace data.

Information processing apparatus

A semiconductor integrated circuit device has a first unit for generating an address and supplying the address to an external device, a plurality of registers for storing predetermined data which designate an address space, a plurality of comparators, and a second unit. Each of the comparators is used to compare the address output from the first unit and the predetermined data stored in each of the registers. The second unit is used to merge a plurality of outputs of the comparators and to generate an enable signal to activate the external device, when at least one of the outputs of the comparators indicates coincidence between the address and the predetermined data. The semiconductor integrated circuit device makes it possible to activate the external device when at least one of the outputs of the comparators indicates coincidence between the address and the predetermined data.

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Kawasaki, Japan

Koutarou Tagawa