Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Ulsi Systems Co., Ltd.

Elpida Memory, Inc.

Hitachi Microcomputer Engineering, Ltd.

Kousuke Okuyama

Masahiro Moniwa

Kazuhiro Komori

Hiraku Chakihara

Akio Nishida

Katsuhiko Kubota

Makoto Mizuno

Shoji Shukuri

Hisao Katto

Mitsuhiro Noguchi

Takashi Hashimoto

Eiichi Murakami

Keiji Okamoto

Tadanori Yoshida

Yasuhiko Takahshi

Kazuyuki Miyazawa

Masamichi Ishihara

Hidetoshi Iwai

Tetsuro Matsumoto

Yasuhiko Takahashi

Kazumichi Mitsusada

Hiroyuki Uchiyama

Kazumasa Yanagisawa

Hideo Aoki

Toshiaki Yamanaka

Yoshiyuki Kawashima

Yasushi Ishii

Takeshi Sakai

Takayuki Oshima

Kiyonori Oyu

Hizuru Yamaguchi

Ryo Nagai

Kazuyuki Tsunokuni

Teruhisa Ichise

Hiroshi Kujirai

Kan Takeuchi

Takahiro Kumauchi

Yasuhiro Kanamaru

Fumitoshi Ito

Takako Funakoshi

Kazuhiro Hata

Riichiro Takemura

Tomonori Sekiguchi

Kenichi Kuroda

Satoshi Meguro

Hideyuki Matsuoka

Norikatsu Takaura

Kota Funayama

Hiroyasu Ishizuka

Yukiko Manabe

Shuji Ikeda

Shinichiro Kimura

Yasuko Yoshida

Jiro Yugami

Keiichi Yoshizumi

Kazushi Fukuda

Soichiro Hashiba

Kazuo Yoshizaki

Fumiyuki Kanai

Kazunori Umeda

Ken Uchida

Kazushi Tomita

Tsuyoshi Tabata

Koichi Imato

Kohji Yamasaki

Chiemi Hashimoto

Kouichi Kusuyama

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Norio Suzuki

Kozo Watanabe

Kouichi Nagasawa

Yoshiyasu Tashiro

Nobuhiro Kasa

Hideki Aono

Syoji Syukuri

A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Semiconductor memory device and a method of manufacturing the same

The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group

Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device

In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Method of manufacturing a semiconductor integrated circuit device

A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Semiconductor integrated circuit device

Semiconductor device

Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Method for manufacturing semiconductor integrated circuit device

A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.

Semiconductor integrated circuit and nonvolatile memory element

Growing community of inventors

Kawagoe, Japan

Kousuke Okuyama