Applied Materials, Inc.

Koushik Ragavan

Anantha R Sethuraman

Raman K Nurani

Karanpreet Aujla

Implementations described herein generally relate to improving silicon wafer manufacturing. In one implementation, a method includes receiving data from one or more manufacturing tools about a manufacturing process of a silicon wafer. The method further includes determining, based on the data, predictive information about a quality of the silicon wafer. The method further includes providing the predictive information to a manufacturing system, wherein the predictive information is used to determine whether to take corrective action.

Predictive modeling of metrology in semiconductor processes

Implementations described herein generally relate to improving silicon wafer manufacturing. In one implementation, a method includes receiving information describing a defect. The method further includes identifying a critical area of a silicon wafer and determining the probability of the defect occurring in the critical area. The method further includes determining, based on the probability, the likelihood of an open or a short occurring as a result of the defect occurring in the critical area. The method further includes providing, based on the likelihood, predictive information to a manufacturing system. In some embodiments, corrective action may be taken based on the predictive information in order to improve silicon wafer manufacturing.

Data management and mining to correlate wafer alignment, design, defect, process, tool, and metrology data

A method and system for determining a defect in a critical area in a multi-layer semiconductor substrate is disclosed. A server receives information describing a defect on a first layer of the semiconductor substrate. The server identifies a critical area of a second layer below the first layer of the semiconductor substrate determines a probability of the defect migrating from the first layer to the critical area of the second layer. The server determines, based on the probability, the likelihood of an open or a short occurring as a result of the defect occurring in the critical area. The server provides, based on the likelihood, predictive information to a manufacturing system, wherein corrective action is taken based on the predictive information in order to reduce or eliminate the likelihood of the open or short.

Method of predicting areas of vulnerable yield in a semiconductor substrate

Implementations described herein generally relate method for detecting excursions in time-series traces received from sensors of manufacturing tools. A server extracts one or more time series traces and metrology data collected from one or more sensors associated with one or more manufacturing tools configured to produce a silicon substrate. The server identifies one or more candidate excursions of the one or more time series traces by comparing the one or more time series traces to one or more traces associated with a working reference sensor. The server verifies that a candidate excursion of the one or more candidate excursions is a true excursion based on correlating the one or more time series traces to the metrology data. The server instructs a manufacturing system to take corrective action to remove the selected true excursion.

Semiconductor process control method

A method for detecting a design-impacting defect in an integrated circuit substrate is disclosed. In one implementation, a controller determines a distribution of intended geometric features in a design window of the integrated circuit substrate based on proximities of a plurality of points of interest in the design window to the intended geometric features. The controller obtains a set of intended contours from the distribution. The controller obtains a set of imaged contours from one or more images of the integrated circuit substrate. The controller compares the set of imaged contours to the set of intended contours to obtain a set of potential design-impacting defects in the intended geometric features. The controller determines a probability that a potential design-impacting defect from the set of potential design-impacting defects is a valid design-impacting defect. The controller takes a corrective action based on the determined probability.

Using design proximity index and effect-to-design proximity ratio to control semiconductor processes and achieve enhanced yield

Implementations described herein generally relate to detecting excursions in intended geometric features in an integrated circuit substrate. In one implementation, a method includes determining a set of suspect contours in a design window of the integrated circuit substrate based on proximities of a plurality of points of interest in the design window to intended geometric features. The method further includes obtaining a set of imaged contours from one or more images of a defect-free integrated circuit substrate. The method further includes comparing the set of imaged contours to the set of suspect contours to obtain a set of potential excursions from the imaged contours. The method further includes determining a probability that a potential excursion from the set of potential excursions is a valid excursion. The method further includes taking a corrective action based on the determined probability.

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Chennai, India

Koushik Ragavan