Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Kousaku Yano

Noboru Nomura

Yoshiaki Kato

Hiroshi Masuda

Shinichi Domae

Tetsuya Ueda

Yuka Terai

Satoshi Ueda

Tomoyasu Murakami

Shuji Hirao

Masayuki Endo

Yuichiro Yamada

Naoki Suzuki

Takashi Uehara

Tatsuo Sugiyama

Michinari Yamanaka

Akemi Kawaguchi

Ryuzo Houchin

Hideko Okada

Hiroshi Yamamoto

Shinji Odanaka

Masafumi Kubota

Shinichi Imai

Hiroshi Imai

Hiroyuki Umimoto

Shinji Fujiwara

Tsutomu Fujita

Eiichiro Tanaka

Masanori Fukumoto

Yasuo Mizuno

Naoto Matsuo

Atsuhiro Yamano

Takao Kakiuchi

Shinji Fujii

Yoshitaka Aoki

Shuichi Tanimura

Staoshi Ueda

Tetauya Ueda

A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.

Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation

Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation

Layer forming material and wiring forming method

Method of producing multilayer wiring device with offset axises of upper and lower plugs

An integrated circuit having a multi-layered metal wiring structure with interlayer insulating films therebetween. A small cutout is made in a metal wiring when it is desirous to have the metal wiring touch a contact formed in a through hole passing through said cutout. A larger cutout is made in a metal wiring when it is desirous to have the metal wiring remain spaced from a contact formed in a through hole passing through said cutout.

Semiconductor device and its manufacturing method

There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for ccntact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.

Semiconductor device comprising MISFETS and method of manufacturing the

A forming apparatus of a thin film, includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate, and a feeding device, which is provided in the processing chamber, for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film, includes steps of forming a thin film on a surface of a supplied substrate in a processing chamber, and feeding material for forming an organic molecular layer including silicon or germanium on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.

Apparatus and method for forming thin film

There are provided the steps of: forming a connection hole in an interlayer insulating film overlying a lower metal interconnection; forming a W plug in the connection hole; forming a first metal film and a second metal film over the interlayer insulating film and the W plug; forming an interconnection underlying film by using a photoresist mask with no alignment margin; and forming a diffusion preventing film made of a titanium fluoride or the like over the W plug, while etching away the exposed part of the first metal film. Reciprocal diffusion of tungsten and aluminum is prevented by the titanium fluoride or the like, thereby preventing the formation of an alloy having high electric resistivity. As a result, an alloy having high electric resistivity resulting from the reaction between the metal plug and the upper metal interconnection is prevented from being formed and a semiconductor device which is high in reliability and integration is provided through the manufacturing process involving no alignment margin.

Method of preventing diffusion between interconnect and plug

A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: ##STR1## wherein X.sub.1 and X.sub.2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y.sub.1, Y.sub.2 and Y.sub.3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R.sub.1 and R.sub.2 is any of SiF.sub.3, SiH.sub.3, CF.sub.3 and CH.sub.3 for example.

Multi-layer wiring structure having varying-sized cutouts

Growing community of inventors

Osaka, Japan

Kousaku Yano