Hewlett-packard Development Company, L.P.

Google Inc.

Compaq Computer Corporation, Inc.

Digital Equipment Corporation

Compaq Information Technologies Group, L.p.

Kourosh Gharachorloo

Luiz Andre Barroso

Andreas Georg Nowatzyk

Robert J Stets, Jr

Mosur Kumaraswamy Ravishankar

Daniel J Scales

Simon C Steely, Jr

Madhumitra Sharma

Stephen R Van Doren

Richard Eugene Kessler

Deborah Anne Wallach

Fay Wen Chang

Jeffrey Adgate Dean

Sanjay Ghemawat

David Asher

Gokul Rajaram

Peter J Bannon

Niels Provos

Victor Bennett

Thukalan V Verghese

Shrish Agrawal

Jayesh Sharma

Phillip M Jones

Stephen R VanDoren

Chester W Pawlowski

Razvan Surdulescu

Luiz Andr&eacute; Barroso

Anshu Aggarwal

A system and method for verifying content on a network site is provided. A document such as a website is identified. The document is accessed over a network from a content provider system connected to the network to obtain information about the document. Through an automated process, using the information about the document to determine whether the document conforms to one or more predetermined rules associated with the content provider system governing the usage of content in the document.

Method and system for using a network analysis system to verify content on a website

In general, systems and methods for identifying anomalous activity are described. For example, systems and methods are described, in which patterns of unusual behavior can be identified by aggregating logged, or sampled, data into cells and annotating each cell with statistically derived measures of how extreme the cell is relative to, for example, historical behavior of corresponding characteristics or relative to, for example, behavior of characteristics from a general population. Cells that have more than a predefined number of such annotations can be identified as anomalous and can be investigated by a user or outright acted upon in an automatic, pre-defined way.

Detecting anomalies

Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.

Techniques for reducing castouts in a snoop filter

When searching a document database in response to a search query, a determination is made as to whether a query result corresponding to the search query is stored in a cache. When the query result is stored in the cache, a reuse count for the search query is accessed. When predefined conditions are satisfied, such as the reuse count being larger than a predetermined threshold count, an improved search result is generated in accordance with a first set of predetermined searching criteria, and at least a subset of the improved search result is returned.

Method and system for query data caching and optimization in a search engine system

A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes. In response to a request for exclusive ownership of a memory line, the protocol engine sends an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.

System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system

When a search query is received, a plurality of partition indexes are searched using the set of search terms in the search query. Each partition index corresponds to a partition of a document index. The search of each respective partition index identifies a subset of a plurality of document index sub-partitions corresponding to the respective partition index. Next, the search query is executed by only those document index sub-partitions identified by the subsets, thereby identifying documents that satisfy the search query. By using the partition index to reduce the number of document index sub-partitions searched while executing a search query, the execution of the search query is made more efficient.

System and method for selectively searching partitions of a database

Once a search query is received from a user, a standard index is searched based on the search query. The standard index forms part of a set of replicated standard indexes having multiple instances of the standard index. A signal is then determined based on the search of the standard index. When the received signal meets predefined criteria, an extended index is searched. The extended index forms part of a set of extended indexes having at least one instance of the extended index. There are fewer instances of the extended index than instances of the standard index. Extended search results are then obtained from the extended index and at least a portion of the extended search results is transmitted towards a user.

System and method for searching an extended database

A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.

Fault containment and error recovery in a scalable multiprocessor

A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA&#x2122; processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRAHNA&#x2122; system, is a highly integrated processing node with eight simpler ALPHA&#x2122; processor cores. A method for scalable chip-multiprocessing is also provided.

Scalable architecture based on single-chip multiprocessing

A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.

Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants

A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block. Eviction of a memory block copy held by an Owner processor in its cache requires a write of the memory block copy to its Home and update of the corresponding coherence directory. No reads of the Home processor directory or modification of other processor cache and main memory is required. The coherence controller in each processor is able to send and receive messages out of order to maintain the coherence of the shared data in cache and main memory. If an out of order message causes an incorrect next program state, the coherence controller is able to restore the prior correct saved program state and resume execution.

Scalable directory based cache coherence protocol

To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.

Method and system for exclusive two-level caching in a chip-multiprocessor

L cache synonyms in a two-level cache system are detected and resolved by logic in the L cache. Duplicate copies of the L cache tags and state (&ldquo;Dtags&rdquo;) are maintained in the L cache. After a miss occurs in the L cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L cache are searched for synonyms. If a synonym is found, the L cache notifies the L cache where the requested cache line can be found in the L cache. The L cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L cache.

Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy

The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.

Growing community of inventors

Menlo Park, CA, United States of America

Kourosh Gharachorloo