Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Maxell, Limited

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Engineering Co., Ltd.

Vlsi Engineering Corporation

Kouki Noguchi

Yasushi Akao

Shumpei Kawasaki

Keiichi Kurakazu

Shigeki Masumura

Shiro Baba

Kaoru Fukada

Mitsuru Watabe

Eiji Sakakibara

Takashi Tsukamoto

Kiyoshi Matsubara

Takanaga Yamazaki

Toshimasa Kihara

Yugo Kashiwagi

Masahiro Kainaga

Yoichi Asano

Katsuhiko Ishida

Yasuhiro Tawara

Shuya Fujita

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Hideo Nakamura

Atsushi Hasegawa

Hiroshi Ohsuga

Yoshitaka Ito

Akio Hayakawa

Yoshimune Hagiwara

Mitsuru Akizawa

Kanji Kato

Masaharu Kubo

Ryo Fujita

Kazufumi Suzukawa

Terumi Sawase

Yasuhiko Takahashi

Michihiro Mishima

Osamu Kubo

Isamu Mochizuki

Hajime Akimoto

Takehisa Hayashi

Toshiaki Masuhara

Toru Baji

Tetsuya Nakagawa

Kazuhiko Iwasaki

Motonobu Tonomura

Mitsuru Hiraki

Atsushi Hatakeyama

Takashi Tsunehiro

Yoshio Sakai

Hitoshi Matsushima

Susumu Narita

Masaru Kokubo

Nobukazu Kondo

Hiromichi Fujisawa

Kei Suzuki

Shigeru Shimada

Shinya Ohba

Tadahiko Nishimukai

Ryo Nagai

Makoto Hanawa

Hirokazu Aoki

Masao Hotta

Kiyokazu Nishioka

Hisamitsu Kawaguchi

Itaru Nonomura

Yuji Hatano

Tsuneya Kurihara

Masahiro Abe

Fumio Tsuchiya

Noboru Yamaguchi

Hirotsugu Kojima

Ryuuji Shibata

Takafumi Kikuchi

Haruo Koizumi

Shuichi Yamamoto

Hiroyuki Masuda

Shigehiro Kamejima

Minoru Ishii

Kazumasa Kishi

Osamu Shinbo

An electronic circuit device has a high-density mount board (), on which are disposed a microcomputer () and random access memory () which are connected to each other through an exclusive memory bus () for high-speed data transfer, a programmable device () which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory () which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Electronic circuit device

An electronic circuit device has a high-density mount board, on which are disposed a microcomputer, a random access memory, a programmable device which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so as to be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device is simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized is simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.

Integrated circuit and information processing device

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals

A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal

Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals

A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Branch instruction having different field lengths for unconditional and conditional displacements

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Kokubunji, Japan

Kouki Noguchi