Renesas Electronics Corporation

Nec Electronics Corporation

Koujirou Matsui

Tomoaki Uno

Kazuyuki Umezu

Takehiko Sakamoto

A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Semiconductor device

A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.

Semiconductor device with shield line disposed between capacitors

In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor deviceincludes a first gate electrode, a fourth source/drain region, and a shared contact electrically connecting the both, wherein in a section taken along the gate length direction, the first gate electrodeand the fourth source/drain regionare disposed as being apart from each other, an element-isolating insulating filmis formed over the entire surface of a semiconductor substrateexposed therebetween, and the distance between the first gate electrodeand the fourth source/drain regionis made substantially equal to the width of the sidewall formed on the side face of the first gate electrode, when viewed in another section taken along the gate length direction.

Growing community of inventors

Kanagawa, Japan

Koujirou Matsui