Fujitsu Corporation

Fujitsu Vlsi Limited

Tii Industries, Inc.

Kouji Ueno

Toshitaka Fukushima

Kazumi Koyama

Tamio Miyamura

Yuichi Kawabata

Yuji Tsuchimoto

Yoshiyuki Fujita

Takeshi Fukuda

Yasurou Matsuzaki

Kazuo Tanaka

Hiroyuki Fujimoto

Tomohiro Nakayama

Yasuro Matsuzaki

Raymond D Jones

Yutaka Fukutani

Masakazu Kimura

Takanori Shiga

John Napiorkowski

Nobuo Ikuta

Toru Mano

Yoshitaka Nakajima

Takamitsu Naito

Kouji Shishido

Youji Arayama

A semiconductor integrated circuit device with a copy-preventive function comprises a memory for storing data to be used by users, an input unit for performing various logical operations on at least one input information fed externally and accessing the memory, an output unit for performing various logical operations on the data at the time of supplying the data from the memory, a judging unit for comparing at least one of the state of the input information, the logical state of the input unit, the logical state of the output unit, and the state of data provided by the output unit with specific judgment information and indicating the result of comparison, and a control unit that when the result indicated by the judging unit reveals that the at least one of the states is consistent with a specific state, acts at least on the output unit so as to prevent data stored in the memory from being supplied normally. Due to this configuration, a copy-preventive function can be reformed frequently from both the aspects of software and hardware. Consequently, illegal copying of data can be substantially disabled.

Semiconductor integrated circuit device with copy-preventive function

A programmable memory device includes memory cells arranged at cross points of word lines and bit lines, a selecting part for selectively decreasing potentials of the word lines, and a writing part for selectively supplying programming currents to the memory cells via the bit lines. Programming current absorbing transistors have first terminals respectively connected to the word lines, second terminals set at a predetermined potential, and bases, and a common load element connected between a node and a programming voltage line. A plurality of base current supplying circuits, which are respectively coupled to the programming current absorbing transistors and connected in common to the node, turn ON the programming current absorbing transistors related to word lines selected by the selecting part so that base currents pass from the programming voltage line to the bases of the programming current absorbing transistors via the common load element and the base current supplying circuits.

Programmable memory device having programming current absorbing

A programmable device has a cell formation region having rows and columns of programmable cells arranged in a matrix arrangement, a real cell region within the cell formation region and constituted by the programmable cells which are to be actually programmed, a test bit region within the cell formation region and including a number of rows of the programmable cells so as to include all kinds of the programmable cells within the real cell region, and a test word region within the cell formation region and including a number of columns of the programmable cells so as to include all kinds of the programmable cells within the real cell region. All of the programmable cells within the real cell region can essentially be tested by testing the programmable cells within the test bit region and the test word region.

Programmable device and method of testing programmable device

A programmable semiconductor memory circuit comprises a memory cell array, a write circuit which is driven by a first power source voltage only in a write mode for writing data into memory cells of the memory cell array, an address input circuit which is driven by a second power source voltage for supplying an address signal to the memory cell array, and an input level correcting circuit supplied with the first power source voltage only in the write mode for supplying the first power source voltage to the address input circuit. The second power source voltage has a voltage higher in the write mode than in a read mode. The address input circuit has an arrangement such that an input threshold value thereof changes when the second power source voltage changes. The input level correcting circuit supplies the first power source voltage to the address input circuit to pull up a signal level at an input of the address input circuit in the write mode so that a signal having a high logic level at the input of the address input circuit is greater than the input threshold value of the address input circuit.

Programmable semiconductor memory circuit

A semiconductor memory device using a junction short type programmable element comprises an epitaxial layer formed on a semiconductor substrate, the epitaxial layer having an opposite conductive type to that of the semiconductor substrate, the epitaxial layer being a collector region; a base region having the same conductive type as the substrate formed in the epitaxial layer; a first emitter region having an opposite conductive type to that of the base region, formed in the base region; an insulating isolation region, formed in said epitaxial layer and around the base region; a second emitter region having a higher impurity concentration than that of the first emitter region and the same conductive type as the of the first emitter region, formed in the first emitter region in such a manner that the second emitter region penetrate the first emitter region upward and downward and extends to the interior of the base region (14) so that a writing current flows concentratedly at the second emitter region.

Semiconductor memory device using junction short type programmable

A memory device comprises an access circuit for setting a selected one of word lines to a low (or high) level responsive to a row address and for setting a selected one of bit lines to a high (or low) level responsive to a columnm address so as to designate a memory cell within a memory cell array, a comparing circuit driven by a constant current source for reading out information from the designated memory cell via the bit lines by comparing the bit line level with a reference level, an output circuit for outputting the information read out by the comparing circuit, and a control circuit for either setting all of the word lines and bit lines to a high level or setting all of the word lines and bit lines to have a high impedance and setting the impedance at an output of the output circuit to a high impedance when the memory device is disabled, so as to reduce the power consumption when the memory device is disabled.

Semiconductive memory device with current control and comparison means

An electronic circuit device, such as an integrated circuit device, includes circuit portions which are not all used at the same time, for example, ECL-type circuits and TTL-type circuits. The electronic circuit device includes at least one power terminal commonly provided for all of the circuit portions and a control circuit for activating part of the circuit portions in accordance with the potential of a power source voltage applied to the power terminal or terminals.

Electronic circuit device having a power supply level switching circuit

A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.

Semiconductor memory device utilizing multi-stage decoding

A semiconductor memory device includes control circuits which are at least a switching circuit and program circuits provided with a constant current source. The switching circuit is mainly comprised of an input side transistor and an output side transistor in the form of a thyristor, and both transistors are on only when a write operation is conducted by the program circuits and the constant current source. If no write operation is conducted, these transistors are both off.

Semiconductor memory device having switching circuit for preventing

A junction short-circuiting-type programmable read-only memory (PROM) device comprises a plurality of striped buried layers (12) and a plurality of striped collector regions (13) thereon. In each of the collector regions, a plurality of base regions (15-0.about.15-5) are disposed in a row, and in each of the base regions one emitter region (16-0.about.16-5) is disposed. Further, in each of the collector regions, a plurality of high impurity regions (17'-1.about.17'-3) of the same conductivity type as the collector region, are formed respectively connected to the word lines, while each base region is connected to one bit line. Each of the high impurity regions are arranged for every two base regions.

Junction short-circuiting-type programmable read-only memory device

A field programmable device comprises a plurality of word lines, a plurality of bit lines which are disposed in a manner to intersect the word lines, a plurality of cells which are respectively connected to the word lines and the bit lines, and a plurality voltage supply means, each of comprising a series connection of a resistor and a diode whose cathode is connected to each of the word lines. The voltage supply means supplies non-selected the word lines with a voltage high enough to prevent parasitic P-N-P-N elements, which are formed by the cells and the word lines, from turning on. Thus a programming current is hindered from flowing out of the cells.

Field programmable device

When a side of a hole formed in a layer of a semiconductor device is located on a slope of a step-like portion, the side of the hole is formed so that it has a wave shape. A conductor line traverses the wave side of the hole.

Contact structure of semiconductor device

A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and alternately arranged conducting and nonconducting test memory cells arranged at the intersections of the test bit lines and the regular word lines. According to the invention, for the purpose of determining poor insulation between the word lines, the test bit line and the regular word line are insulated by an insulating layer in each nonconducting test memory cell.

Field programmable device with circuitry for detecting poor insulation

A field programmable device comprising a memory cell part and a plurality of test bit rows provided along bit lines of the memory cell part and/or a plurality of test word rows provided along word lines of the memory cell part. At least one of the rows of the test bit and/or test word rows is written-in with a write-in ratio different than those of the other test bit and/or test word rows.

Field programmable device with internal dynamic test circuit

A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.

Growing community of inventors

Kawasaki, Japan

Kouji Ueno