Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Kouji Takada

Masami Yokozawa

Satoru Takahashi

Seiki Yamaguchi

Hiroyoshi Yoshida

Shigeki Sakaguchi

Yuji Tanaka

Masahiro Yasohara

Kazuyuki Takada

Yasushi Kato

Ryutaro Arakawa

Shinichi Emura

A overheat protection circuit is formed on the same semiconductor substrate as a power MOS FET is formed on. As the configuration, a first resistor is connected between an input terminal and a gate of the power MOS FET, a second resistor, a temperature sensing element, and a third resistor are connected in this order between the input terminal and a ground point, an FET for clamp is connected in parallel to a series circuit of the temperature sensing element and the third resistor, a series circuit of an FET for current adjustment and a fourth resistor is connected in parallel to the MOS FET for clamp, a series circuit of a fifth and sixth resistors is connected between the input terminal and the ground point, a node of the fifth and sixth resistors is connected to a gate of the FET for current adjustment, an FET for switching is connected between the gate of the power MOS FET and the ground point, and a node of the temperature sensing element and the third resistor is connected to a gate of the FET for switching.

Semiconductor device provided with overheat protection circuit and electronic circuit using the same

In a semiconductor switch, a voltage detection circuit is provided so as to be in parallel with a first switching element for turning on/off a power supply to a load, in which a voltage detection portion for detecting a drain voltage of the first switching element by dividing a voltage upon a resistance ratio or the like and a second switching element are connected in series to each other. The second switching element is turned on/off in accordance with ON/OFF of the first switching element. Accordingly, detection of a drain voltage is performed normally when the first switching element is in an ON state. When the first switching element is in an OFF state, a leakage current can be reduced by the second switching element.

Semiconductor switch having a voltage detection function

A load driving device capable of preventing thermal destruction even when a load short-circuit or an overcurrent occurs, thereby having improved reliability, is provided. A load driving device, in which a power switch element for driving a load and a circuit for controlling the power switch element according to a signal V supplied from the outside are formed on one chip, is provided with an OFF-time delaying circuit for delaying an OFF-time transition of a level of an input signal at which the power switch element makes the transition from an ON state to an OFF state, according to a result of detection of a current flowing through the load and the level of the input signal to the power switch element.

Load driving device

A lead frame used for a resin-sealed semiconductor device includes a die-mount portion on which a semiconductor chip rests; and a plurality of leads arranged along a common portion of the lead frame. The plurality of leads include at least one adjusting lead, and the adjusting lead has a length that is less than the others of the plurality of leads such that a tip of the adjusting lead is sufficiently proximate to an outer peripheral surface of a resin-seal body to prevent resin flash during a formation of the semiconductor device and to allow the adjusting lead to be removed after the resin-seal body is formed over a portion of the lead frame.

Method for producing a resin-sealed semiconductor device

Lead frame, mold for producing a resin-sealed semiconductor device, resin-sealed semiconductor device using such a lead frame

A PWM inverter output circuit enabling circuit integration, having a fast response characteristic, and unaffected by dv/dt transients is provided. A predrive circuit 17 drives a power circuit 11 comprising first and second power elements P1 and P2 by controlling the gate and source potential of the power elements P1 and P2 based on a stored control state. The control state is detected from a logic signal output from an input signal processor 13, which converts a command signal instructing turning on and off the power elements P1 and P2 to predetermined logic signals. Operating power is drawn from a main dc power source V1, a control power source V2, and a power supply capacitor C1 that is charged using an output voltage from the control power source V2. The gates and sources of the power elements P1 and P2 are connected together.

PWM inverter with zero dead time and initial power supply capacitor

Growing community of inventors

Kameoka, Japan

Kouji Takada