Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Kouji Okamoto

Hiroki Mouri

Akira Yamamoto

Takashi Morie

Akira Kawabe

Yoshito Hirai

Fumiaki Senoue

Takashi Yamamoto

Shiro Dosho

Heiji Ikoma

Youichi Ogura

Yoshinori Shirakawa

Michiko Tokumaru

Toshihiko Takahashi

Shiro Sakiyama

Hitoshi Kobayashi

Masao Hamada

Akio Yokoyama

Hirokuni Fujiyama

Kouichi Nagano

Kazuaki Sogawa

Yuji Yamada

Kazutoshi Aida

Hideki Nishino

Kiyotaka Tanimoto

Kouhei Nakata

Disclosed is a distortion-compensation apparatus that can reduce the storage space for storing coefficients required for distortion-compensation calculation, and can accurately execute distortion compensation. Distortion-compensation apparatus () compensates for distortion of an output signal from a predetermined circuit by predistortion in which an input signal is preliminarily multiplied by a coefficient. First multiplication section () of distortion-compensation apparatus () multiplies an input signal by a first coefficient selected from coefficient candidates in accordance with the input signal; second multiplication section (to) multiplies a delay signal of an input signal by a tap coefficient; and adding section () outputs a signal obtained by adding together an input signal multiplied by the compensation coefficient and the delay signal multiplied by the tap coefficient to the predetermined circuit.

Distortion-compensation device and distortion-compensation method

Disclosed is a distortion compensation apparatus that, by appropriately generating a distortion-compensation coefficient, makes it possible to obtain a desired transmission output, and substantially reduce the amount of power leakage to an adjacent channel. Reception section () of the distortion compensation apparatus acquires and demodulates a transmission signal to generate a demodulation signal. Delay adjustment section () computes the delay amount of the demodulation signal with respect to the baseband signal, eliminates the delay of the demodulation signal with respect to the baseband signal based on the delay amount, and outputs the baseband signal and the demodulation signal in which the delay is eliminated. Distortion compensation section () determines a distortion compensation coefficient in an adaptive digital predistortion process based on the baseband signal and the demodulation signal output by delay adjustment section (), and multiplies the input signal by the distortion compensation coefficient.

A storage unit stores a first lookup table including a plurality of correction coefficients for I codes, and stores a second lookup table including a plurality of correction coefficients for Q codes. Each of the correction coefficients for I codes and each of the correction coefficients for Q codes are complex numbers. A distortion compensation unit compensates, with one of the plurality of correction coefficients for I codes, distortion of an I code of a transmission signal to generate a first input signal, outputs the first input signal to an SCPA for I codes. The distortion compensation unit compensates, with one of the plurality of correction coefficients for Q codes, distortion of a Q code of the transmission signal to generate a second input signal, and outputs the second input signal to an SCPA for Q codes.

Transmission device and distortion compensation method

A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time &#x394;&#x3a3; A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time &#x394;&#x3a3; A/D converters to feed back the digital signal to the digital filter.

Actuator driver

In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.

Digital PLL circuit and communication device

In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.

Digital PLL circuit, semiconductor integrated circuit, and display apparatus

A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Filter circuit, semiconductor integrated circuit, communication apparatus, semiconductor device, and system

Filter circuit, transmission filter circuit, semiconductor integrated circuit, communication apparatus, and timing adjustment method for filter circuit

A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.

Receiver, signal processing apparatus, and video display apparatus

In a synchronous reproduction signal processor, when a phase error between reproduction data and a clock is repeatedly detected such that a clock synchronized with a reproduction signal is generated based on the phase error, a filtering process unit () performs a filtering process which performs a weighed addition with respect to a phase error series prior to the current time from a phase error calculation unit () using, e.g., a FIR filter with a plurality of taps so as to generate a reference value under reduced influence of noise mixed in the phase error series by feedback correction. A cross detection unit () detects the timing with which the sampled reproduction data crosses the reference value generated by the filtering process unit (). This allows effective use of the dynamic range of the feedbacked reference value without limiting it, and simultaneously achieves the enhancement of noise immunity.

Phase comparator and reproduction signal processor using the same

In a feedforward control type reproduced signal processor, a clock generatorchanges a clock frequency, depending on a digital value set by a digital value generator. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculatorsatisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generatorgradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.

Reproduced signal processor and video display

In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation sectioncalculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizerby utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control sectioncontrols the frequency dividing rate of the frequency synthesizerin such a manner that the frequency ratio calculated by the frequency ratio calculation sectionhas a set value. Thus, as compared with a case in which the output clock of the frequency synthesizeris a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.

Timing extractor, and information playback apparatus and DVD device using the timing extractor

When generating a sampling clock of an A/D converter for digitizing a playback signal from an optical disc, an over sampling clock generated by a PLL is used. Further, zerocross position information and reference information of a playback digital signal that is obtained by A/D conversion using the over sampling clock are converted into those synchronized with the channel bit clock by an operation cycle conversion unit, and then supplied to a PRML signal processing unit and a level judgement binarization unit.

Playback signal processing apparatus and optical disc device

In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuitis inputted to a Gm-C filterto be filtered and then converted by a conversion circuitto a digital signal. A reference signal RS from the reference signal generation circuitis converted by a conversion circuitto a digital signal. The two converted signals are held in time series in a holding circuit. A timing generation circuitgenerates an update timing signal en based on a reference time-series signal ref from the holding circuitA control signal generation circuitgenerates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit. The control signal CS is inputted to the Gm-C filterin response to the update timing signal en to adjust the gain of the Gm-C filter. As a result, variations in the response characteristics of the Gm-C filterare adjusted with high accuracy with a simple circuit structure.

Filter adjustment circuit

In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generatorinputs, as a rising cross reference value S, rising phase error data Scalculated in a phase error calculatorto a rising cross detectorand inputs, as a falling cross reference value S, falling phase error data Ssimilarly calculated to a falling cross detector. Each of the cross detectorsandcalculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) Sor Sand outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.

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Osaka, Japan

Kouji Okamoto