Panasonic Corporation

Renesas Electronics Corporation

Panasonic Intellectual Property Management Co., Ltd.

Socionext Inc.

Matsushita Electric Industrial Co., Ltd.

Denon, Ltd.

Kouji Nakajima

Takeshi Tanaka

Eiji Otomura

Hiroshi Amano

Hideshi Nishida

Takahiro Kageyama

Yoshiaki Tanaka

Keita Mochizuki

Takahiro Korenari

Kensuke Nakashima

Kengo Terada

Manabu Kuroda

Akira Sakamoto

Yoshihiro Koga

Teruyuki Morita

Yoshihiro Nakahara

Keisuke Yorioka

A semiconductor device making it easy to detect disconnection in source wires and achieving a reduction in resistance and an inspection method for the semiconductor device are provided. A semiconductor device according to the present embodiment includes: a lead frame; a semiconductor chip on the lead frame; a source pad provided in the semiconductor chip; a plurality of source wires connected to the source pad; a disconnection detection wire connected to the source pad; source terminals connected to the plurality of source wires; and a disconnection detection terminal connected to the disconnection detection wire. One end of the disconnection detection wire is positioned in vicinity of a corner of the source pad closer to the disconnection detection terminal side.

Semiconductor device and inspection method for semiconductor device

A semiconductor device includes a control unit which controls charging/discharging of a secondary battery, a bidirectional coupling unit which is electrically coupled to the control unit and through which a charging/discharging current flows, and a protection diode coupled between the control unit and the bidirectional coupling unit. The bidirectional coupling unit includes a discharging power transistor, a charging power transistor reversely coupled in series with the discharging power transistor, and a common drain pad which functions as a drain of the discharging power transistor and further functions as a drain of the charging power transistor. An anode of the protection diode is electrically coupled to the common drain pad. A cathode of the protection diode is electrically coupled to a power supply terminal of the control unit.

Semiconductor chip, semiconductor device and battery pack

A semiconductor device includes a first main MOS transistor and a second main MOS transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode and a first sense MOS transistor and a second sense MOS transistor of a vertical structure that are inversely coupled to each other in series by sharing a drain electrode. The first sense MOS transistor is used for detecting the main current of the first main MOS transistor, and the second sense MOS transistor is used for detecting the main current of the second main MOS transistor.

Semiconductor device and overcurrent protection device

To provide a semiconductor product high in versatility. A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board.

With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16&#xd7;16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate an many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

Video decoding device, video decoding method, video decoding program, and video decoding integrated circuit

A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src, src, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Very-long instruction word (VLIW) processor and compiler for executing instructions in parallel

With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16&#xd7;16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate as many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

A computer system includes: a main storage unit, a processing executing unit sequentially executing processing to be executed on virtual processors; a level-1 cache memory shared among the virtual processors; a level-2 cache memory including storage areas partitioned based on the number of the virtual processors, the storage areas each (i) corresponding to one of the virtual processors and (ii) holding the data to be used by the corresponding one of the virtual processors; a context memory holding a context item corresponding to the virtual processor; a virtual processor control unit saving and restoring a context item of one of the virtual processors; a level-1 cache control unit; and a level-2 cache control unit.

Multi-threaded processor context switching with multi-level cache

Very long instruction word (VLIW) computer having efficient instruction code format

Flexibility for the design of the pattern layout of the gate lead-out electrode and the source electrode is enhanced without increasing the chip thickness of the semiconductor device. A semiconductor device includes a cell region where plural transistor cells are arranged and a gate finger region different from a region where the cell region is formed. In the cell region, a gate electrode formed of a polysilicon (first conductive material) is formed. A polysilicon layer formed indivisibly with the gate electrode is formed in the gate finger region. An adhesion metal layer and a wiring metal layer are formed above the polysilicon layer by a lift-off method. The gate lead-out electrode is formed of a laminate structure including the polysilicon layer, the adhesion metal layer, and the wiring metal layer. A single layer of interlayer insulation film covering them is formed, on which a source electrode is formed.

Power semiconductor device including gate lead-out electrode

An address generating unitgenerates a different write start address (w_adr) of a picture memorydepending on an aspect ratio and/or a display plane position of a motion picture to be displayed. A picture writing unitwrites data to the picture memory, starting at the calculated write start address (w_adr). A picture reading unituses the write start address (w_adr) as a read start address (r_adr) and reads data from the picture memory, starting at the read start address (r_adr).

Motion picture display device

An image processing apparatus of the invention includes: a plurality of processing units which share image processing; a parameter memory unit which holds a parameter specifying an operation of each of the processing units; and a control unit which controls the plurality of processing units, and the control unit includes: a sequence management unit which activates each of the processing units according to a sequence indicating a sequence of activation of and completion of processing by each of the processing units, and confirms completion of the processing; and a parameter setting unit which, in advance of activation of each of the processing units by the sequence management unit, reads a parameter for each processing unit to be activated, from the parameter memory unit according to a memory map indicating an address of the parameter for the processing unit, and sets the parameter to the processing unit according to the read result.

Growing community of inventors

Tokyo, Japan

Kouji Nakajima