Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Other

Kouji Hayano

Akira Yamazaki

Katsumi Dosaka

Yasuhiro Konishi

Masaki Kumanoya

Hisashi Iwamoto

Hideaki Abe

Yasuhiro Ishizuka

Katsumitsu Himukashi

Tsukasa Saiki

Tsukasa Saika

A semiconductor memory device is provided with a static random access memory (SRAM) serving as a cache memory and a dynamic random access memory (DRAM) serving as a main memory. A bi-directional data transfer circuit is arranged for transfer of data blocks between the SRAM and the DRAM. A command register is provided for holding command data to set operation modes such as a data output mode of the memory device. The data output mode may include a transparent mode, a latched mode and a registered mode selected depending on a data combination at data input terminals of the memory device. An output circuit for providing a selected data output mode includes an output latch circuit for latching data on read data buses in response to clock signals, and an output buffer for outputting data from the output latches to a data output terminal. The latch circuit provides data at a first clock cycle of a clock signal when the command data has a first value and provides data at a second clock cycle of the clock signal, which is later than the first clock cycle, when the command data has a second value.

Synchronous semiconductor memory including register for storing data input and output mode information

A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

Semiconductor memory device

A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

Semiconductor memory device with an internal voltage generating circuit

A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

Semiconductor memory device and data transfer circuit for transferring data between a DRAM and a SRAM

A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.

Semiconductor memory device including a data transfer circuit for

A semiconductor integrated circuit device includes an internal circuit and a power-on reset signal generation circuit. The internal circuit includes an output node and an input for a power-on reset signal. The potential of the output node becomes indefinite immediately after the power-up. The internal circuit also has a function of forcing the potential of the output node to a high level in response to the power-on reset signal being applied for a sufficiently long period of time. The power-on reset signal generation circuit has a reset input, an input connected to the output node, and an output connected to the input for the power-on reset signal in the internal circuit. The power-on reset signal generation circuit starts generating the power-on reset signal in response to input of a reset signal, and stops the generation of the power-on reset signal in response to the potential of the output node attaining the high level. Since the generation of the power-on reset signal is not stopped until the potential of the first output node attains the first level, the internal circuit can surely reset the potential of the output node to the high level.

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Hyogo-ken, Japan

Kouji Hayano