Mitsubishi Denki Kabushiki Kaisha

Kouji Gotou

Takeo Nakabayashi

Hiroshi Kuranaga

Kazuya Ishihara

A semiconductor integrated circuit comprises a timing signal generating circuit for generating a plurality of timing signals in response to an externally applied reference signal, a plurality of sequential circuits to be operated in synchronism with the plurality of timing signals respectively, a plurality of combination circuits provided between the plurality of sequential circuits. Each timing signal to be applied to each sequential circuit is delayed by the time period longer than the difference between the delay amount in a combination circuit at the preceding stage and the period of a reference signal with respect to a timing signal to be applied to a sequential circuit at the preceding stage.

Semiconductor integrated circuit operating in synchronism with a

A main bus and a plurality of sub buses constitute a hierarchical bus. A signal transmission circuit is connected between the main bus and each of the plurality of sub buses. The main bus and the plurality of sub buses are precharged to a predetermined potential. The signal transmission circuit discharges a corresponding sub bus or causes the potential of the sub bus to be maintained in accordance with the potential of the main bus when a first enable signal is at a first logic level. The signal transmission circuit causes the potential of a corresponding sub bus to be maintained when a first enable signal is at a second logic level. The signal transmission circuit discharges the main bus or causes the potential of the main bus to be maintained in accordance with the potential of a corresponding sub bus when a second enable signal is at a first logic level. The signal transmission circuit causes the potential of the main bus to be maintained when a second enable signal is at a second logic level.

Signal transmission circuit and signal transmission method

A transmitter/receiver applicable as an interface circuit in ISDN terminals is disclosed. In externally designated total phase deviation measurement mode, the delay time caused by a receiver circuit and a driver circuit, i.e. a phase difference, is predetected by a phase comparator. The detected phase difference signal is stored in a phase control circuit, and the phase control circuit controls the pahse of a periodical timing signal generated from a PLL circuit. Therefore, as a data buffer applies a transmitting data to the driver circuit 7 in response to the phase control timing signal, the phase difference of the transmitting data signal generated from the driver circuit relative to the received data signal is made to be the minimum.

Transmitter/receiver for generating transmitting data signal in

There are disclosed an FCS encoder responsive to data to be transmitted for generating a frame check sequence (FCS) code to check a transmission error, and an FCS decoder for detecting an error. These FCS encoder and FCS decoder have a division circuit and a multiplication circuit each of which comprises shift registers in 16 stages and EXOR gates. Since there is no need for logical elements to be connected between the respective shift registers, this FCS encoder can be constituted to show a regular circuit layout on a semiconductor substrate.

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Hyogo, Japan

Kouji Gotou