Kabushiki Kaisha Toshiba

Toshiba Computer Engineering Corporation

Kouiti Kanamaru

Junichi Inoue

Akihiko Furuya

A magnetic disk controller incorporating a cache memory which employs an LRU (Least Recently Used) scheme in a replacement algorithm of cache blocks and comprising a directory memory whose entries have LRU counter fields, a host system issuing a read/write command to which an arbitrary LRU settling value is appended, a directory search circuit, and a microprocessor. The directory search circuit searches the directory memory in response to the read/write command issued from the host system. The microprocessor stores the LRU setting value appended to the read/write command in the LRU counter field of the hit entry of the directory memory or of the entry corresponding to the repalacement target cache block, in response to the search result of the directory search circuit.

Cache system used in a magnetic disk controller adopting an LRU system

A cache system employing an LRU (Least Recently Used) scheme in a replacement algorithm of cache blocks and comprising a directory memory whose entires have LRU counter fields, a host system issuing a read/write command to which an arbitrary LRU setting value is appended, a directory search circuit, and a microprocessor. The directory search circuit searches the directory memory in response to the read/write command issued from the host system. The microprocessor stores the LRU setting value appended to the read/write command in the LRU counter field of the hit entry of the directory memory or of the entry corresponding to the replacement target cache block, in response to the search result of the directory search circuit.

Growing community of inventors

Tokyo, Japan

Kouiti Kanamaru