Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

On Semiconductor Trading, Ltd.

Patrenella Capital Ltd., LLC

Kouichi Yamada

Atsushi Wada

Shigeto Kobayashi

Shigeyuki Okada

Yoshitaka Ueda

Mamoru Mukuno

Shigeharu Matsushita

Yoh Takano

Hideaki Fujiwara

Hideaki Miyamoto

Yoshiki Murayama

Naofumi Sakai

Hajime Mizukami

Takashi Asano

Sadao Kondo

A signal line from a common terminal, which allows the insertion of a terminal of a cable for transmitting high-frequency signals or the insertion of a terminal of a cable dedicated to the transmission of audio signals, is branched into one line which is connected to one end of a high-frequency signal switch (USB switch) and the other line which is connected to one end of an audio signal switch (audio switch), respectively. A signal line from the other end of the high-frequency signal switch is connected to a target circuit. A signal line from the other end of the audio signal switch in a primary hierarchical position is branched into a plurality of lines, and the respective plurality of lines are connected to one end of audio signal switches (e.g., headphone switch and microphone switch) in a secondary hierarchical position. And the respective signal lines from the other end of the plurality of audio signal switches of secondary hierarchical position are connected to respective target circuits.

Switch circuit

A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage Vand a second power supply capable of supplying a second power supply voltage V, which is lower than the first power supply voltage V. A first transistor TRis provided between the first power supply and an output node, whereas a second transistor TRis provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR

Power supply circuit

A fourth n-channel MOSFET has a source terminal and a back-gate terminal connected to each other. A switch element is connected between the source terminal of the fourth n-channel MOSFET and a ground potential, and the source terminal of the fourth n-channel MOSFET is made become the ground potential when the fourth n-channel MOSFET is OFF. A protection circuit is provided between a connection node of the source terminal of the fourth n-channel MOSFET and an input terminal of the switch element, and the ground potential so that a negative inflow current from the drain terminal of the fourth n-channel MOSFET caused by electrostatic discharge flows to the ground potential.

Switch and switch circuit using the same

In a bidirectional switch using a metal-oxide-semiconductor field-effect transistor (MOSFET), the source terminal and the backgate terminal of the MOSFET are connected to each other via a transfer gate. A switch may be used between the connection point of the backgate terminal and the transfer gate of the MOSFET and the ground potential (where the MOSFET is an n-channel type) or supply potential (where the MOSFET is a p-channel type).

Bidirectional switch and switch circuit using the bidirectional switch

A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.

Protection circuit and input/output circuit

A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

Semiconductor device

In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.

A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate.

Nonvolatile semiconductor memory device, method for manufacturing the same, and nonvolatile memory array

A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.

Memory

A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.

In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal. At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type.

Double edge triggered flip-flop circuit

A first switch receives an input signal. A second switch receives the input signal, in parallel with the first switch. An output potential sensing inverter detects the potential of an output signal derived from a connection point of the first switch and the second switch. Upon receipt of an output of the output potential sensing inverter, an input switch controls whether the input signal is inputted to the second switch or not. When the potential of the output signal exceeds a predetermined threshold voltage, the output potential sensing inverter performs control such that the input switch be turned off.

Inverter circuit

A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

Memory comprising diode

A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

Growing community of inventors

Gifu, Japan

Kouichi Yamada