Fujitsu Corporation

Kouichi Noro

Tohru Takeshima

Yoshioka Hiroshi

Hideaki Suzuki

Eiichi Nagai

Chika Kayaba

Amane Inoue

Masaji Inami

Shingo Hagiwara

A CTI server receives calls from telephone terminals. The CTI server includes an analysis unit, an icon creating unit, and an icon display control unit. The analysis unit analyzes conditions for a call from a telephone terminal to generate parameter which represents the presumed psychological state of a customer using the telephone terminal. The icon creating unit creates an icon for visually displaying the presumed psychological state of the customer on the basis of the parameters. The icon display control unit for displaying the presumed psychological state of the customer using the icon.

CTI server and program recording medium

Each of a plurality of memory cells includes one ferroelectric capacitor having one terminal connected to a bit line. A plurality of decoder circuits are arranged on each of the plurality of memory cells, and connected to the other terminal of the ferroelectric capacitor forming the memory cells via a plurality of word lines. These plurality of decoder circuits control the word lines to one of high level, low level, and a floating state, thereby writing data in the memory cells or reading out data from the memory cells.

Semiconductor memory and method of controlling the same

In a ferroelectric memory, there are provided a plurality of word lines, a plurality of bit lines crossing there-with, a plurality of memory cells having ferroelectric capacitors arranged at the positions of these crossovers and a plurality of correction capacitors connectable with the bit lines. At least some of the plurality of correction capacitors are connected with a bit line so as to be capable of increasing bit line capacitance by a prescribed amount.

Ferroelectric memory wherein bit line capacitance can be maximized

A semiconductor memory device includes ferroelectric memory cells, cell transistors connected between first nodes of the memory cells and data transfer lines, the memory cells and the cell transistors being grouped into units each corresponding to one or more column addresses, global word lines, one of which is activated in response to selection of a corresponding row address, global plate lines, one of which is activated in response to selection of the corresponding row address, local word lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to gates of the cell transistors, local plate lines, each of which is provided and dedicated for a corresponding one of the units, and is connected to second nodes of the memory cells, and a unit switch circuit which electrically connects the activated one of the global word lines to one of the local word lines in a selected one of the units so as to achieve the same potential therebetween, and electrically connects the activated one of the global plate lines to one of the local plate lines in the selected one of the units so as to achieve the same potential therebetween.

Semiconductor memory device with reduced power consumption and with reduced test time

On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.

Method of manufacturing a semiconductor device having data pads formed in scribed area

A semiconductor memory device has a first ferroelectric memory cell in which data is written after the device is mounted on a board, and a second ferroelectric memory cell whose capacitance is larger than that of the first ferroelectric memory cell. This second ferroelectric memory cell is utilized as a memory cell in which cipher or the like are written in the fabrication process. The second ferroelectric memory cell is formed with a combination of a plurality of the first ferroelectric memory cells. In order to realize the second ferroelectric memory cell, word lines or plate lines corresponding to a plurality memory-cell rows may be short-circuited. Alternatively, bit lines corresponding to a plurality memory-cell columns may be short-circuited.

Growing community of inventors

Kawasaki, Japan

Kouichi Noro