Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Kouichi Nagasawa

Satoshi Meguro

Shuji Ikeda

Yoshio Sakai

Norio Suzuki

Toshiaki Masuhara

Osamu Minato

Isamu Kobayashi

Atsuyoshi Koike

Toshifumi Takeda

Katsuro Sasaki

Masahiro Ogata

Hisahiro Moriuchi

Makoto Motoyoshi

Kikuo Sakai

Ryuuji Shibata

Youichi Matsumoto

Kiyoshi Nagai

Hideo Meguro

Kousuke Okuyama

Yasunobu Kosa

Takashi Aoyagi

Sho Yamamoto

Akihiko Tani

A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

Semiconductor memory device having first and second selecting lines for

After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

Process for fabricating semiconductor integrated circuit devices

Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, the electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

Semiconductor devices and a process for producing the same

A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

Semiconductor memory device

A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses the out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent the lowering of the yield with respect to the electrical reliability. In SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.

Semiconductor device to prevent out-diffusion of impurities from one

A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.

Read-only memory

A static RAM exhibiting a high reliability and suited to a higher density of integration is disclosed. In each memory cell of this static RAM, the cross coupling of a flip-flop circuit is made by gate electrodes of MISFETs constituting this flip-flop circuit. In addition, a source line is formed by the same step as that of a word line. A resistance value of a polycrystalline silicon layer which is a load resistor is changed in accordance with information to be stored. Furthermore, semiconductor regions for preventing soft errors attributed to alpha particles etc. are formed under the MISFETs constituting the flip-flop circuit, so that the channels are not adversely affected.

Semiconductor memory cell device with thick insulative layer

A semiconductor device includes a first conductor layer into which is diffused an impurity for lowering the resistance, and a second conductor layer provided on the upper side of the first conductor layer through a stopper layer which suppresses out-diffusion of the impurity. By virtue of the existence of the stopper layer, it is possible to inhibit the above-described impurity from being diffused into the second conductor layer. In a SRAM, resistance variations between high-resistance elements which correspond to the second conductor layer can be suppressed, so that it is possible to prevent lowering of the yield with respect to the electrical reliability. In a SRAM, further, the resistance of the high-resistance elements is not lowered; therefore, it is possible to reduce the power consumption.

Semiconductor device sram to prevent out-diffusion

Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

Fabricating semiconductor devices to prevent alloy spiking

Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.

Process for fabricating semiconductor integrated circuit device

A process for producing semiconductor devices having excellent electric characteristics such as high threshold voltage Vth and small leakage current, maintaining high yields while preventing the occurrence of thermal etching at the time of heat-treatment to form a well diffusion layer in semiconductor devices such as CMOS IC's. Namely, a semiconductor wafer having a silicon dioxide film formed on the main surface thereof is heat-treated at a high temperature in an inert gas atmosphere. In this case, oxygen is contained in small amounts in the inert gas, so that pinholes formed in the silicon dioxide film are buried therein by the action of oxygen gas. Therefore, thermal etching is not generated by the high temperature inert gas, and the yields of semiconductor devices can be increased.

Process for producing semiconductor devices

Disclosed is a method of manufacturing a semiconductor device which includes MOSFETs of the two-channel conductivity types of P- and N-channel types on a single semiconductor substrate. According to the present invention, a first mask and a second mask are used. The first mask covers that surface part of the semiconductor substrate in which the P-channel type MOSFET is to be formed, and it serves as a mask when an N-type impurity is introduced into the semiconductor substrate. The first mask has a property and etching rate different from those of a film formed by the thermal oxidation of the semiconductor substrate surface. The second mask covers that surface part of the semiconductor substrate which has been formed with the N-channel type MOSFET, and it serves as a mask when a P-type impurity is introduced into the semiconductor substrate. The second mask is used as an inter-layer insulator film.

Method of making CMOS semiconductor device using specially positioned,

Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

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Kunitachi, Japan

Kouichi Nagasawa