Kabushiki Kaisha Toshiba

Kouichi Kurihara

Shuji Abe

Kenji Shimoda

Seiichi Tanaka

Shinji Yoda

Takeshi Inagaki

Takashi Koga

A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on tracks of a prescribed recording medium and playbacks them, includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding them in variable length code, a data rearrangement canceller for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data rearrangment canceller.

Variable length code recording/playback apparatus

An encoded data recording apparatus with high speed reproduction capability, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

Variable length code recording playback apparatus

A coding data is performed in decoding by a stream decoding circuit, an IDCT circuit and an MC circuit. An AGU stores decoding data from the MC circuit to a memory. Regarding the decoding data of a B picture, the AGU writes only the decoding data which are necessary for image display, to a B picture region. Thus, a room occurs in a memory capacity. It is possible to hold the decoding data of the B picture through 2 field periods of time. It is possible to read twice the same decoding data, for display processing. Thus, frame interpolation processing is made possible, and it is possible to obtain a magnified image having high image quality.

Image decoding using read/write memory control based on display region

A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearrange for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

Encoding data are given to a variable-length decoding circuit and are decoded, and are given to a memory so as to be stored therein. The same data are read out from the memory, whereby decoding processing of the encoding data is executed twice within one frame period. Decoding data due to the twice decoding processings are stored in the memory at an output part thereof. Data of odd fields are read out in display order in the first half of the display period of one frame. Data of even fields are read out in display order in the latter half of the display period of one frame. Thus, even in case where restored image data of a B-picture are outputted in interlacing, a memory capacity can be reduced.

Image decoding with dedicated bidirectional picture storage and reduced

A read control circuit reads image data, which are stored in a decoding image memory, at a read speed m/n times a display speed. These image data are written to line memories by a write control circuit. A read-address control circuit reads the image data from the line memories at a display speed, and line data for a letter-box image are generated by multipliers and an adder. Specifically, the line data of m lines which are read from the decoding image memory are transformed to n lines so that a letter-box display is made possible. Thus, letter-box transformation processing is performed with less memory capacity without the use of a field memory.

Letter-box transformation device

A variable length code recording/playback apparatus, which by encoding intra-frame data and inter-frame data in variable length code, records them as recorded codes on prescribed locations of tracks of a recording medium and plays them back, which includes a data rearranger for recording the data in areas to be played back at least two specific speed mode playbacks on the tracks by rearranging prescribed data out of the data encoded in variable length code, a variable length decoder for playing back the data recorded on the recording medium and decoding it in variable length code, a data restorer for controlling and restoring the time series of the output of the variable length decoder to the original data train before the rearrangement, and a decoder for constructing a playback picture from the decoded outputs for several frames in the specific speed mode playback by decoding the output of this data restorer.

A decoding output of a B-picture is given to a memory. A memory control circuit divides a one (1) image plane to four (4) regions. Write is executed to the memory for the divided image data that are the decoding output with respect to eight (8) regions of first and second fields. The time at which each of the divided image data are retained in the memory is decided in accordance with the field to which the divided image data belongs and a position on an image plane. On the basis of this, subsequent to the readout of the divided image data, the other divided image data are written to a common storage region of the memory. Thus, a total memory capacity is reduced to enable interlacement conversion.

Image decoding apparatus

A motion detecting circuit for a video signal processor having a filter arrangement for separating the video signal into the low and high frequency components, a first detecting circuit for detecting a low frequency luminance moving signal, a second detecting circuit for detecting a high frequency luminance moving signal, a third detecting circuit for detecting a chrominance moving signal, a first threshold circuit for generating a low band luminance motion digit signal, a second threshold circuit for generating a high band luminance motion digit signal, a control circuit coupled for generating a control signal in response to the low and high band luminance motion digit signals, a gate circuit for selectively transmitting the chrominance moving signal in response to the control signal and a selector for selectively outputting the one of the low frequency luminance moving signal and the chrominance moving signal having the high signal intensity.

Motion detecting circuit for video signal processor

A picture quality improving apparatus includes a multiplexer for multiplexing a digital luminance signal and a digital color difference signal upon reception thereof and outputting a first multiplex signal. A noise reduction circuit reduces a noise component from the first multiplex signal and outputs a second multiplex signal. A motion detector receives the first multiplex signal and detects a picture movement signal included in the first multiplex signal. An interpolation signal generator generates a first interpolation signal based on the digital luminance signal and generates a second interpolation signal based on the second multiplex signal. A signal selector selects one of the first and second interpolation signals from the interpolation signal generator in accordance with the picture movement signal detected by the motion detector.

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Tokyo, Japan

Kouichi Kurihara