Fujitsu Corporation

Kouichi Kitano

Tsuyoshi Matsumoto

Hideaki Isogai

Junichi Sawada

Atsuhiko Utsumi

Kenichi Ishikawa

A generating unit generates an apparatus reference frame phase that becomes a reference in a data multiplexing/demultiplexing apparatus, based on a reception frame phase of the data input to a predetermined reception buffer and a predetermined delay amount. A multiplexing/demultiplexing unit reads data from the reception buffer based on the apparatus reference frame phase generated by the generating unit, and multiplexes or demultiplexes the data.

Method and apparatus for multiplexing and demultiplexing data, and computer product

A transmission system provides a stand-by line switching facility. The transmission system includes a plurality of working line side processing equipments and a stand-by line side processing equipment to replace one of the working line side processing equipments if a fault occurs therein. The transmission system has a first unit and second unit disposed for each working line side processing equipment. The first unit issues, upon receipt of a line switching command, a single line switching control signal. The second units commonly receive the single line switching control signal and respective line switching is performed between the faulty working line and the stand-by line simultaneously.

Transmission system having stand-by line switching facility

A word-line discharging circuit in a static-type semiconductor memory device, including, for each word line, a first transistor for detecting the potential change of the word line, a time-constant circuit for delaying the output of the first transistor, and a second transistor for conducting a discharging current through the memory cells. The second transistor is switched in response to the output of the time-constant circuit, and includes, for all of the word lines, a common discharging current source. The word-line discharging circuit further includes means respectively provided between the word lines and the common discharging current source for respectively slowing the rate of change in the current flowing through the word lines, whereby double selection of the word lines is prevented.

Word-line discharging circuit in a static-type semiconductor memory

A semiconductor memory circuit including a charge absorbing circuit. The charge absorbing circuit absorbs at least a current induced by a voltage increase in the word line occurring soon after the word line is switched from a selection state to a nonselection state.

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Kawasaki, Japan

Kouichi Kitano