Fujitsu Corporation

Fujitsu Semiconductor Limited

University of Toronto

Kouichi Kanda

Hirotaka Tamura

Junji Ogawa

Hisakatsu Yamaguchi

Satoshi Matsubara

Shoichi Masui

Kazuaki Oishi

Takuji Yamamoto

Yasuhiro Watanabe

Ali Sheikholeslami

Tetsuji Yamabana

Hidetoshi Matsumura

Jun-ichi Nagata

Shiho Nakahara

Nobumasa Hasegawa

Xiao-Yan Wang

Mohammad Bagherbeik

Xiongchuan Huang

A method includes: calculating a change amount of energy of an Ising model, the change amount being caused when values of four states are changed, for each of a plurality of first states having a value of 0 before change, so as to satisfy a constraint that a sum of values of states included in each row is 1, and a sum of values of states included in each column is 1, when N (an integer of 2 or larger) squared state variables included in an evaluation function representing the energy of the Ising model are arrayed in N rows and N columns; selecting the four states allowed to change by using the change amount calculated for each of the plurality of first states, and outputting identification information for identifying the four states; and updating values of the four states allowed to change by using the identification information.

Optimization device and optimization method

A method includes: accessing first storage configured to store a first weight coefficient group which is at least some of a plurality of weight coefficients indicating a magnitude of interaction between a plurality of state variables in an evaluation function representing energy of an Ising model; accessing a plurality of second storages each of the plurality of second storage being configured to store a second weight coefficient group related to a state variable having a value of 1 in any of a plurality of state variable groups respectively including the plurality of state variables among the plurality of weight coefficients; outputting, for each of the plurality of state variable groups, a search result obtained by performing searching processing configured to perform processing of searching for an optimum solution by repeatedly performing a first update process with a first constraint or a second update process with a second constraint.

Optimization apparatus and optimization method

According to an aspect of an embodiment, operations may include obtaining a first matrix associated with an optimization problem associated with a system and obtaining a second matrix associated with the optimization problem. The operations may include obtaining a local field matrix that indicates interactions between the variables of the system as influenced by their respective weights. The operations may include updating the local field matrix. Updating the local field matrix may include performing arithmetic operations with respect to a first portion of the first matrix and a second portion of the second matrix that correspond to a third portion of the local field matrix that corresponds to the one or more variables. The operations may include updating an energy value of the system based on the updated local field matrix and determining a solution to the optimization problem based on the energy value.

System local field matrix updates

An optimization device includes: k first calculation circuits, N&#x2212;k second calculation circuits, a selection circuit, an identification information calculation circuit and an update circuit. The first calculation circuit calculates a first energy change of an Ising model due to a change of a value of one of k first bits having values of 1 and a change of a value of a second bit having a value of 0 selected based on a generated first random number. The second calculation circuit calculates a second energy change of the Ising model due to a change of a value of one of (N&#x2212;k) third bits having the values of 0 and a change of a value of a fourth bit having a value of 1 selected based on a generated second random number.

Optimization device and control method of optimization device

An information processing device includes: a memory; and a processor coupled to the memory and configured to calculate, for a plurality of bits corresponding to a plurality of spins included in an Ising model obtained by converting a problem to be calculated, in a case where the plurality of bits is divided into a plurality of groups, on the basis of a first local field value for a first bit having a value of 1 and a second local field value for a second bit having a value of 0 among a plurality of bits included in each of the plurality of groups, a first energy change of the Ising model due to a change of the value of the first bit from 1 to 0 and a change of the value of the second bit from 0 to 1.

Optimization device and method for controlling optimization device

An optimization device includes a plurality of calculation circuits; a selection circuit; an identification information calculation circuit, and an updating circuit. Each of the plurality of calculation circuits calculates, for a plurality of bits corresponding to a plurality of spins included in an Ising model obtained by converting a problem to be calculated, a first energy change of the Ising model due to a value of a first bit having the value of 1 being changed from 1 to 0 and a value of a second bit having the value of 0 being changed from 0 to 1. The selection circuit outputs first bit identification information identifying one second bit having a value permitted to be updated from 0 to 1, based on a magnitude relationship between thermal excitation energy and the first energy change output by each of the plurality of calculation circuits.

A position detection system includes a GNSS sensor terminal that receives a satellite signal from a GNSS satellite as a snapshot, at least one relay device that receives the snapshot GNSS signal transmitted by the GNSS sensor terminal, and a calculation device that measures a position of the GNSS sensor terminal by using a code phase and a Doppler frequency of the GNSS satellite obtained from the snapshot GNSS signal, wherein the calculation device estimates an initial position of the GNSS sensor terminal by using position information of the relay device that has received the snapshot GNSS signal transmitted by the GNSS sensor terminal.

Position detection system, position detection device, position detection method, and sensor terminal

A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.

Clock recovery circuit, semiconductor integrated circuit device, and radio frequency tag

A sensor device includes: a first portion that is formed of an inorganic semiconductor material, includes a control module, and is reusable; a second portion that is formed of an organic material and separably coupled to the first portion; and a sensor that is disposed in at least one of the first and second portions.

Sensor device for wearable device generating power-on trigger signal

A clock regeneration circuit includes a pattern detection circuit that detects a pattern having a time interval determined in advance in an input signal, and a signal processing circuit that generates a clock by variably controlling a time interval for oscillation based on the time interval of the detected pattern.

Clock regeneration circuit, semiconductor integrated circuit device and RF tag

A flip-flop circuit includes a data capture circuit that captures data based on a clock, a data hold circuit that holds an output of the data capture circuit based on the clock, and a timing control circuit that controls coupling between the output of the data capture circuit and the data hold circuit based on the clock, when the data capture circuit captures new data based on the clock, the timing control circuit performing control so as to temporarily interrupt the coupling between the output of the data capture circuit and the data hold circuit.

Flip-flop circuit and semiconductor integrated circuit device

A clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.

Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag

A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Power amplifier circuit and semiconductor integrated circuit

A semiconductor integrated circuit includes a first transmission power mode configured to transmit by a first power, and a second transmission power mode configured to transmit by a second power smaller than the first power, the semiconductor integrated circuit. The semiconductor integrated circuit includes a first transistor configured to receive and amplify a transmission signal in the second transmission power mode, and an attenuator including a resistor element and a switching element, provided between an output of the first transistor and an output terminal, configured to control attenuation of an output signal of the first transistor.

Semiconductor integrated circuit and wireless transmitter

A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.

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Chofu, Japan

Kouichi Kanda