Sony Corporation

Koninklijke Philips Corporation N.v.

Other

Asahi Kasei Kabushiki Kaisha

Kouhei Yamamoto

Toshiyuki Miyauchi

Masayuki Hattori

Takashi Yokokawa

Marten Erik Van Dijk

Jun Murayama

Tatsuya Narahara

Hiroyuki Kishi

Josephus A H M Kahlman

Constant P M J Baggen

Sho Sugiyama

Naoto Yabuki

Ludovicus M G M Tolhuizen

Susumu Senshu

Masayuk Hattori

An ultraviolet irradiation device having higher processability and interfacial adhesiveness, and allowing downsizing is provided. The ultraviolet irradiation device includes an enclosure configured to include a hollow portion being formed inside and being capable of introducing an irradiation object, an outer periphery of the enclosure being covered by a covering portion, and a light source configured to be arranged in an area not covered by the covering portion of the enclosure and project light toward the hollow portion. The covering portion is formed of thermoplastic resin fiber. Processability and interfacial adhesiveness can be improved by forming the covering portion with thermoplastic resin fiber. Consequently, a structure advantageous for downsizing of the ultraviolet irradiation device is provided.

Ultraviolet irradiation device

A method of embedding an additional layer of error correction into an error correcting code, wherein information is encoded into code words of said code over a first Galois field and wherein a number of code words are arranged in the columns of a code block comprising a user data sub-block and a parity data sub-block, provides an additional layer of error correction that can be easily implemented without losing compatibility improving the error correction capabilities. The method includes the steps of:

Method and apparatus for embedding an additional layer of error correction into an error correcting code

A method of embedding an additional layer of error correction into an error correcting code, where information is encoded into code words that are arranged in columns of a code block. The method includes reducing the length of each row of the code block by adding row symbols together according to a predetermined adding rule resulting in a reduced code block; encoding the shortened rows of the reduced code block using a horizontal error correcting code to obtain horizontal parities; and embedding the horizontal parities as additional layer in the error correcting code.

To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit () in each element decoder includes a received value and a priori probability information selection circuit () to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (), the received value and a priori probability information selection circuit () replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is '0'. That is, the received value and a priori probability information selection circuit () outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is '0' or &#x201c;1&#x201d; to be &#x201c;&#xbd;&#x201d;.

Soft-output decoding

A decoder that receives, as input, probability information AMP/C&#xd7;y. This probability information is obtained by dividing a channel value obtained by multiplication of received value yand a predetermined coefficient AMP by the first additive coefficient Cfor regulating the amplitude of the received value yand the probability information 1/C&#xd7;APPobtained by multiplying the a priori probability information APPby the reciprocal of the second additive coefficient Cfor regulating the amplitude of the a priori probability information APPto a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output C&#xd7;I&#x3bb;and/or external information 1/C&#xd7;EXusing additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

Decoder an decoding method

Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is '&#x2154;' as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is '1' as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.

Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein

To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatusis designed so that an interleaverinterleaves order of bits so that all weights are coded by a convolutional coderwith respect to data comprising a series of 3 bits supplied from a convolutional coder; the convolutional codermakes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver; and a multi-value modulation mapping circuitcauses the hamming distance of input bits in the convolutional coderas the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coderto mapping.

A decoder has a reduced circuit dimension that does not adversely affect the decoding performance of the circuit. The decoder includes an addition/comparison/selection circuit added to give the log likelihood and adapted to compute a correction item expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.

Decoder and decoding method

Multiword information is based on multibit symbols disposed in relative contiguity with respect to a medium, and is encoded with a wordwise interleaving and wordwise error protection code for providing error locative clues across multiword groups. In particular, the clues originate in high protectivity clue words (BIS) that are interleaved among clue columns, and also in synchronizing columns constituted from synchronizing bit groups. The synchronizing columns are located where the clue columns are relatively scarcer disposed. The clues are directed to low protectivity target words (LDS) that are interleaved in a substantially uniform manner among target columns which form uniform-sized column groups between periodic arrangements of clue columns and synchronizing columns.

Growing community of inventors

Tokyo, Japan

Kouhei Yamamoto