Matsushita Electric Industrial Co., Ltd.

Matushita Electric Industrial Co., Ltd.

Kouei Misaizu

Hiroshi Ohnishi

Akihiko Matsuoka

Yuuri Yamamoto

Mitsuo Makimoto

Morikazu Sagawa

Yoshinori Kunieda

Masayuki Orihashi

Makoto Hasegawa

Kazuaki Takahashi

Hiroshi Onishi

Kenichi Takahashi

Makoto Takemoto

Haruyoshi Endo

Shoichiro Honda

Nonlinear distortion compensating data is calculated by approximation equations at a compensating coefficient calculation section using an amplitude value of transmission quadrature base band signals obtained by a power calculating section, wherein by carrying out nonlinear distortion compensation at a nonlinear distortion compensating section using the data, it is possible to compensate nonlinear distortion generated in an amplifier of the transmission system without use of any memory table, and a nonlinear distortion compensating section can be obtained, which has a great effect of decrease distortion.

Transmission Apparatus

In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.

Frame synchronizing apparatus for quadrature modulation data

An input bit sequence is converted into n-bit parallel symbol signals each representing one symbol. A shift register stores an 'm' number of the n-bit parallel symbol signals, shifting the n-bit parallel symbol signals one symbol by one symbol and outputting them. At least one selector is operative for sequentially selecting one of the k-th symbol signal and the (m+1)-k-th symbol signal outputted by the shift register in response to a clock signal, where k equals 1, 2, . . . , (m-1)/2. A sampling counter serves to count pairs of successive clock pulses of the clock signal. An Exclusive-OR circuit executes Exclusive-OR operation between the clock signal and an output signal of the sampling counter. At least one first read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts. A second read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts. A filter output signal is generated by combining the data output by the first read-only memory and the second read-only memory.

Nyquist filter for digital modulation

A frequency conversion circuit for mixing first and second frequency signals to supply an output frequency signal comprises: first and second FETs having first and second gates for receiving the first and second frequency signals respectively; and a third FET having a third gate ac-grounded, the first to third FETs being connected in series such that a current flowing through the current circuit between the source and drain is controlled by the first to third gates, the third FET being provided between the first and second FETs. The third FET may also be provided between connection an end of the series connector and the second FET in accordance with frequency differences between the first and second frequency signals and between the second frequency signal and the output frequency signal. A triple gate FET can be used in place of these three FETs connected in series. A quad gate FET can be used also. A mixing circuit including the frequency conversion circuit mentioned above is also disclosed.

Frequency conversion circuit and mixing circuit including the same

A diversity receiver includes a first antenna and a second antenna. A first receiving section connected to the first antenna serves to convert a digital modulation wave induced at the first antenna into a first intermediate-frequency signal. A first band pass filter connected to the first receiving section serves to subject the first intermediate-frequency signal to a band pass filtering process. A second receiving section connected to the second antenna serves to convert a digital modulation wave induced at the second antenna into a second intermediate-frequency signal. A second band pass filter connected to the second receiving section serves to subject the second intermediate-frequency signal to a band pass filtering process. A switch alternately selects one of output signals of the first and second band pass filters at a period equal to a half of a period corresponding to the symbol rate. A quadrature demodulator connected to the switch serves to demodulate an output signal of the switch into quadrature baseband signals. An analog-to-digital converter connected to the quadrature demodulator converts the quadrature baseband signals into corresponding digital signals. A decision feedback adaptive equalizer connected to the analog-to-digital converter serves to subject the digital signals to an equalizing process.

Diversity receiver

A terminal unit apparatus for a time division multiplexing access radio communications system formed of a base station and a number of terminal units remote from the base station, includes a 2-dimensional adaptive equalizer circuit for equalizing two quadrature-relationship baseband signals which are obtained from a received quadrature digital modulation signal during receiving operation of the terminal unit, and an internal signal source which generates a local oscillator signal for use in demodulating a received signal to obtain these baseband signals. A frequency correction quantity is derived from the average rate of variation in each symbol interval of the ratio of the two main tap coefficients of the 2-dimensional adaptive equalizer circuit, and used to correct the frequency of operation of the internal signal source during both receiving operation and also in transmitting operation, in which the internal signal source provides a carrier signal for modulation. Frequency correction can thereby be achieved that is independent of the effects of multi-path interference to the transmission path upon the received quadrature digital modulation signal.

Terminal unit apparatus for time division multiplexing access

An asynchronous quadrature demodulator which comprises an asynchronous quadrature detector, a frequency compensating circuit for estimating and compensating a frequency offset between an oscillating frequency of a local oscillator of the asynchronous quadrature detector and a frequency of a received carrier frequency on the basis of correcting signals, a base band complex equalizer for eliminating a transmission-channel distortion due to a multiplex transmission and a data demodulator. Thereby, a reference carrier recovery circuit becomes unnecessary. Thus, the structure of the demodulator can be simplified. Further, the demodulator can stably operate on the transmission channel.

Asynchronous quadrature demodulator

A mixer for outputting an intermediate frequency signal as the result of mixing of a radio frequency signal and a local oscillator signal which are inputted into the mixer. The mixer comprises a balanced-to-unbalanced conversion circuit and a bridge-coupled diode circuit and the balanced-to-unbalanced conversion circuit is constructed of first and second rat race circuits, one being for the radio frequencey signal and comprising a first ring-shaped line and the other being for the local oscillator signal and comprising a second ring-shaped line. The mixer is arranged to include a substrate having first and second pattern-forming surfaces and the first ring-shaped line of the first rat race circuit is formed as a pattern on the first pattern-forming surface of the substrate and the second ring-shaped line of the second rat race circuit is formed as a pattern on the second pattern-forming surface. The bridge-coupled diode circuit is positioned on the first pattern-forming surface thereof and inside the patterned first ring-shaped line.

Mixer with rat race circuit

A microwave band frequency synthesizer comprises first and second phase-locking loops. The first phase-locking loop includes a first voltage controlled oscillator, a variable frequency divider and a first multiplier and generates an output signal whose frequency changes at the rate of a unit frequency change width of the oscillator. The second phase-locking loop includes a first fixed frequency divider for frequency-dividing the output signal of the first phase-locking loop to provide a phase comparison reference signal of a frequency higher than that phase-compared in the first phase-locking loop, a second voltage controlled oscillator, a second fixed frequency divider for frequency dividing an output of the second voltage controlled oscillator, a second phase comparator for phase-comparing a frequency-divided an output signal of the second fixed frequency divider and the phase comparison reference signal in order for phase-locking of the second voltage controlled oscillator, and a second multiplier for multiplying the output signal from the second voltage controlled oscillator to provide a microwave band signal.

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Kawasaki, Japan

Kouei Misaizu