Amic Technology Corporation

Advanced Micro Devices Corporation

Kou-Su Chen

Shih-Chun Fu

Jui-Te Chan

David K Liu

Vei-Han Chan

David K Y Liu

Sai-Keung Lee

A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from &ldquo;fast&rdquo; bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Method for manufacturing non-volatile memory cell array

Method for operating non-volatile memory cells

Circuit and method for equalizing erase rate of non-volatile memory cells

System and method for erasing non-volatile memory cells

Circuit and method for pre-erasing/erasing flash memory array

A circuit and method for achieving an improved pre-programming of flash memory cells is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for hot electron pre-programming operations. By eliminating the need to pre-program the memory array with hot electrons, the invention provides a signicant improvement for flash arrays, because device life and reliability is extended. In addition, pre-programming time and power is reduced significantly since the operation takes place on a sector (parallel) basis rather than a single bit line (serial) basis, and a charge pump is not needed to generate the current injected into floating gates of cells in the sector.

Flash memory cell & array with improved pre-program and erase characteristics

A novel erase mechanism using junction hot hole injection is disclosed for flash memory cell sector and bulk erase operations. A constant current supply is used so that a suitable junction voltage breakdown can be provided despite expected variations in cell structures, operations, etc. The inventive method eliminates the need for dual polarity voltage supplies for erase operations, and provides a method to achieve a tight distribution of erased cell threshold voltages. In addition, over-erasure problems associated with Fowler-Nordheim tunneling are essentially eliminated.

Flash EPROM using junction hot hole injection for erase

A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from 'fast' bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Circuit and method for conditioning flash memory array

A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Circuit and method for erasing flash memory array

A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.

Circuit for detecting both charge gain and charge loss properties in a

A simple edge-triggered flip-flop is provided that does not require a clock or a master-slave structure. In some embodiments, the flip-flop has multiple set, reset and/or trigger (T) inputs.

Edge-triggered flip-flop

A constant time delay circuit which is insensitive to variations in temperature and has no D.C. power disipation includes a temperature-insensitive reference current source (12) for dynamically charging and discharging a capacitive load (M5), a polysilicon resistor (16), and at least one time delay control circuit (14) to produce a constant time delay. In an alternate embodiment, there is provided a temperature self-compensated programmable delay circuit which includes electrically programmable resistor means (30) for adjusting the total resistance in a temperature-insensitive reference current source (12b). As a result, the amount of the reference current is controlled so as to obtain a desired delay time.

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Fremont, CA, United States of America

Kou-Su Chen