Renesas Electronics Corporation

Nec Electronics Corporation

Kou Sasaki

Tomohiro Kamimura

Tomoharu Inoue

Takashi Yonezawa

A semiconductor package includes a package board, a pellet provided over the package board, and a protection member covering the package board and the pellet and including a hole penetrating the protection member.

Semiconductor package and system

A semiconductor apparatus capable of detecting a crack generated in a semiconductor chip while the design freedom, the layout freedom of a wiring, the layout efficiency of LSI, and the layout efficiency of a package substrate are improved. The semiconductor apparatus according to the invention includes a semiconductor chip having a multilayered wiring structure; plural electrode pads being formed on a top surface along the outer periphery of the semiconductor chip; and a wiring being coupled to a first electrode pad and a second electrode pad selected from the plural electrode pads and formed along the entire outer periphery of the semiconductor chip in plan view. The wiring includes a first wiring and a second wiring that are formed on different layers, and the first wiring and the second wiring are connected in series by a connection plug.

Semiconductor apparatus

Even when only one of semiconductor packages mounted by carrying out infrared reflow is defective, it is required to carry out infrared reflow again to dismount this defective semiconductor package from a mounting board. At this time, stress of heat is also applied to the other non-defective semiconductor packages. For this reason, if infrared reflow is carried out beyond a number of times of infrared reflow specified for non-defective semiconductor packages, the operation of each non-defective semiconductor package cannot be assured. In this case, it is inevitable to discard the semiconductor packages together with the mounting board. To solve this problem, a magnetic material is passed through a hole penetrating a protection member and a package board and the relevant semiconductor package is fixed over a mounting board by this magnetic material. To supply power to the semiconductor package, electromagnetic induction by coils provided in the package board and the mounting board is used.

A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes.

Semiconductor package land grid array substrate and plurality of first and second electrodes

A first memory chip () and a second memory chip () mounted in this order on one surface of a mounting board () each have a rectangular planar shape and include a plurality of electrode pads formed in a single line along one side of the rectangle. An electrode pad line of the second memory chip () is formed in parallel with an electrode pad line of the first memory chip (). A chip select pad is disposed on an end of the electrode pad line. Control pads, address pads, or data pads () of the first memory chip () are wire bonded to first stitches () formed in a single line along one side of the rectangle. A chip select pad () and a chip select pad () are wire bonded to second stitches () formed in a line along a side adjacent to a side of the chip select pad (). Accordingly, an increase in package area is suppressed when a plurality of memory chips are stacked.

Semiconductor device including mounting board with stitches and first and second semiconductor chips

A semiconductor device package includes a plurality of stacked semiconductor chips and a spacer interposed therebetween. The spacer includes a first spacer and a second spacer stacked on one another. The first and the second spacers have different principal surfaces. If the second spacer has a larger principal surface than the first spacer, flexure of the upper semiconductor chip can be avoided.

Semiconductor device package of stacked semiconductor chips with spacers provided therein

A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity concentration of the first channel regions, a third step of forming a plurality of third channel regions in a third region on the surface of the water, and a fourth step of forming a plurality of fourth channel regions having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region, wherein the first region and the second region are divided by a first line segment on the wafer, and the third and fourth regions are divided by a second line segment intersecting with the first line segment on the wafer.

Sample wafer fabrication method

A semiconductor apparatus capable of simply detecting a crack generated in plural semiconductor chips while the design freedom is improved, includes a first semiconductor chip and a second semiconductor chip that is laminated on the first semiconductor chip, in which a first wiring that is formed along the outer periphery of the first semiconductor chip and a second wiring that is formed along the outer periphery of the second semiconductor chip are connected in series.

Growing community of inventors

Kanagawa, Japan

Kou Sasaki