International Business Machines Corporation

Kotb Jabeur

John Kenneth DeBrosse

Daniel Christopher Worledge

Pouya Hashemi

Jonathan Zanhong Sun

Matthew R Wordeman

Dimitri Houssameddine

Ryan A Jurasek

Eric Robert Joseph Edwards

A method for compensating for external magnetic fields in memory devices that includes positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, wherein a write driver is in electrical communication with at least one external magnetic field sensing element and at least one array of memory cells. The at least one external magnetic field sensing element is monitored for signals indicative of the present of an external magnetic field. The write current to the at least one array of memory cells can be adjusted by trimming the write driver to operate the memory device while compensating for the external magnetic field.

Write driver with magnetic field compensation

A magnetic tunnel junction (MTJ) device includes a cylindrically-shaped pillar structure and a first ferromagnetic layer disposed on at least a portion of the pillar structure. The first ferromagnetic layer exhibits a magnetization that is changeable in the presence of at least one of an applied bias and heat. The MTJ device further includes a dielectric barrier disposed on at least a portion of the first ferromagnetic layer and a second ferromagnetic layer disposed on at least a portion of the dielectric barrier. The second ferromagnetic layer exhibits a magnetization that is fixed. The MTJ device is configured such that the first and second ferromagnetic layers and the dielectric barrier concentrically surround the pillar structure.

Magnetic tunnel junction having all-around structure

Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.

Dynamic boosting techniques for memory

An MRAM bitline write control circuit including an MRAM array of a plurality of MTJ cells. Each MTJ cell is connected to a bitline between a bitline transfer gate and a transfer device. Each transfer device is connected to a sourceline and a sourceline transfer gate. A master bitline is connected to each bitline transfer gate. A first bitline control transistor is connected to VDD and to a source follower transistor that is connected to the master bitline and a gate connected to a write 0 bias voltage. A second bitline control transistor is connected to VSS and to the master bitline. A selected MTJ cell is biased to write a 0 when the transfer device, the bitline transfer gate and the source line transfer gate, associated with the selected MTJ cell, are enabled and the first bitline control transistor is enabled to connect the source follower transistor to VDD.

MRAM bit line write control with source follower

A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.

Dynamic redundancy for memory

A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blof the second subset of the reference memory bit cells outputs a read reference signal.

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Essex Junction, VT, United States of America

Kotb Jabeur