Hitachi, Ltd.

Hitachi Ome Electronic Co., Ltd.

Kotaro Nishimura

Satoshi Meguro

Nobuyoshi Tanimura

Tokumasa Yasui

Shuji Ikeda

Sho Yamamoto

Osamu Minato

Shinji Shimizu

Akira Endo

Toshio Sasaki

Masaharu Kubo

Yoshio Sakai

Toshiaki Masuhara

Minoru Fukuda

Osamu Yamashiro

Koichi Nagasawa

Hiroshi Fukuta

Kanji Yoh

Harumi Wakimoto

Kazutaka Narita

Shigeru Yamatani

Yukio Sasaki

A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Semiconductor memory having a polycrystalline silicon load resistor and

Semiconductor memory having polycrystalline silicon load resistors and

This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other. The channels of the first and second IGFETs have an identical conductivity type. On the basis of a self-alignment structure, at least those parts of first and second polycrystalline semiconductor regions being the gate electrodes of the first and second IGFETs which are proximate to source and drain regions are doped with the same impurity as that of the source and drain regions, and a central part of one of the first and second polycrystalline semiconductor regions is doped with an impurity of a selected one of the first conductivity type and the second conductivity type.

Reference voltage generator device

An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Semiconductor memory device

An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Method for making static random-access memory device

The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch elements. The paired transfer gate elements are controlled on a switch in complementary manner each other according to a transfer signal. The first switch element is controlled on a switch according to the transfer signal, and the second switch element is controlled on a switch according to the first signal transmitted to one of the paired transmission lines. The first switch element turns one of the transmission lines to a fixed potential like ground potential when it is kept on, and the second switch element turns the other of the transmission lines to a fixed potential when it is kept on. The line change-over circuit in the above configuration is effective to prevent a floating state of the paired transmission lines.

Line change-over circuit and semiconductor memory using the same

An electrically programmable read only memory includes a plurality of non-volatile memory elements having control gates which are commonly connected to a first word line and drains which are coupled to a write-down circuit for supplying a write-down voltage to said drains. To prevent the flow of leakage current caused by parasitic capacitance, at least one of source electrodes of the plurality of non-volatile memory elements is connected to ground potential through the drain-source path of a first switch MISFET whose gate electrode is connected to the first word line. When a word line driving signal of non-selection level is applied to the first word line, the first switch MISFET is non-conductive. Thus, leakage current is prohibited from flowing through the first switch MISFET. Further, in order to prevent deterioration of the rewrite-down efficiency of the memory, the write-down circuit includes a pn-junction element having a junction characteristic which is substantially equal to the drain junction characteristic of the non-volatile memory elements. The level of a write-down voltage to be applied to the drains of the non-volatile memory element is determined on the basis of the reverse breakdown voltage of the pn-junction element. Thus, the breakdown of the drain junction of the non-volatile memory elements during a write-down operation can be prevented, so that deterioration of the rewrite-down efficiency of the electrically programmable read only memory can be prevented.

Electrically programmable read only memory having reduced leakage current

Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.

Memory circuit with increased operating speed

On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

Semiconductor device

In a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and first and second MOSFETs connected in series between a clock pulse terminal and ground. The first MOSFET conducts in response to the terminal voltage of the capacitor to transmit a clock pulse from its drain and supplies an output to a word line. The terminal voltage of the capacitor in one decoder is applied to the gate of the second MOSFET of another decoder and the word line output of the other decoder is grounded even during the discharging period of the capacitor in the non-selection mode of the other decoder, enabling a synchronous supply of the address and the clock pulses.

MIS decoder providing non-floating outputs with short access time

In a sensing amplifier for a capacitive MISFET memory, the level of an output signal from the memory is shifted by a signal level shifting circuit and the level-shifted signal is applied to an input of the sensing amplifier to thereby provide a high speed operation.

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Kokubunji, Japan

Kotaro Nishimura