Taiyo Yuden Co., Ltd.

Kotaro Mizuno

Yoichi Kato

Yukihiro Konishi

Hidetoshi Masuda

Yusuke Kowase

Shohei Kitamura

Masaru Kurosawa

Toru Makino

Daigo Ito

Daisuke Sakate

Yoshinori Tanaka

Chie Kawamura

Taisei Irieda

Kazumichi Hiroi

Ayumu Sato

Kazuki Yamada

Jun Nishikawa

Yosuke Sato

Katsuya Taniguchi

Yasunari Kato

Sachie Tomizawa

Yuichi Kasuya

Kazushi Yawata

Joji Kobayashi

Toshimitsu Kogure

Koichi Tsukagoshi

Takehiro Tanaka

Hidenori Wakayanagi

A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers each including Ni as a main phase are alternately stacked. At least one of the dielectric layers includes Si. One of the internal electrode layers next to the at least one of the dielectric layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In. A peak of a concentration of the additive element and/or a peak of a concentration of Si in the one of the internal electrode layers and the at least one of the dielectric layers exist(s) in a region within 15 nm in a thickness direction from an interface between the one of the internal electrode layers and the at least one of the dielectric layers.

Ceramic electronic device and manufacturing method of the same

A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers are alternately stacked. In an outermost one of the internal electrode layers, a metal oxide containing a main component element constituting the internal electrode layers is provided on an outer main surface of the outermost one, and a formation depth of the metal oxide is 0.5 μm or more and 5.0 μm or less. A segregation layer containing a sub metal element different from the main component metal is present at an interface between at least one of the internal electrode layers other than the outermost one and one of the dielectric layers adjacent to the at least one of the internal electrode layers.

Ceramic electronic device

An all solid battery includes: a solid electrolyte layer of which a main component is oxide-based solid electrolyte; a first electrode layer that is provided on a first main face of the solid electrolyte layer and includes an active material; and a second electrode layer that is provided on a second main face of the solid electrolyte layer and includes an active material, wherein at least one of the first electrode layer and the second electrode layer includes an aggregate of carbon particles and a cavity, wherein the aggregate demarcates at least a part of the cavity.

All solid battery

A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 μm in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.

Multi-layer ceramic capacitor

A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers of which a main component is ceramic, and each of a plurality of internal electrode layers are alternately stacked. The plurality of internal electrode layers include Ni, S and Sn.

Ceramic electronic device, powder material, paste material, and manufacturing method of ceramic electronic device

A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers including Ni as a main phase are alternately stacked. At least one of the plurality of dielectric layers includes a secondary phase including Si, at an interface between the at least one of the plurality of dielectric layers and one of the plurality of internal electrode layers next to the at least one of the plurality of dielectric layers. The one of the plurality of internal electrode layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In, at a region contacting the secondary phase at the interface.

A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.

Manufacturing method of multilayer ceramic electronic device

A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.

A multi-layer ceramic capacitor includes: a multi-layer unit including ceramic layers laminated in a first direction and electrodes disposed between the ceramic layers, positions of end portions of the electrodes falling within a range of 0.5 &#x3bc;m in a second direction; and side margins each containing manganese or magnesium and silicon and facing each other in the second direction. When each margin is equally divided into an inner region and an outer region, a total concentration of manganese and magnesium in the outer region is higher than a total concentration of manganese and magnesium in the inner region and higher than a total concentration of manganese and magnesium in the ceramic layers, and a concentration of silicon in the inner region is not less than a concentration of silicon in the outer region and higher than a concentration of silicon in the ceramic layers.

A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.

An all solid battery includes a multilayer chip in which each of a plurality of solid electrolyte layers including solid electrolyte and each of a plurality of internal electrodes including an electrode active material are alternately stacked, the multilayer chip having a rectangular parallelepiped shape, the plurality of internal electrodes being alternately exposed to two side faces of the multilayer chip other than two end faces of a stacking direction of the multilayer chip, and a pair of external electrodes that contacts the two side faces and include solid electrolyte.

All solid battery and manufacturing method of the same

An all solid battery includes a multilayer chip in which each of a plurality of solid electrolyte layers including solid electrolyte and each of a plurality of internal electrodes including an electrode active material are alternately stacked, the multilayer chip having a rectangular parallelepiped shape, the plurality of internal electrodes being alternately exposed to two side faces of the multilayer chip other than two end faces of a stacking direction of the multilayer chip, and a pair of external electrodes that contacts the two side faces. At least one of the pair of external electrodes includes an electrode active material of which a pole is a same as that of an electrode active material of the internal electrode which contacts the one of the pair of external electrodes.

An all solid battery includes a solid electrolyte layer, a first electrode structure that has a structure in which a first electric collector layer of which a main component is a conductive material is sandwiched by two first electrode layers including an active material, and a second electrode structure that has a structure in which a second electric collector layer of which a main component is a conductive material is sandwiched by two second electrode layers including an active material. Roughness of interfaces between the first electric collector layer and the two first electrode layers and/or roughness of interfaces between the second electric collector layer and the two second electrode layers is larger than roughness of interfaces between the solid electrolyte layer, and the first electrode layer and the second electrode layer sandwiching the solid electrolyte layer.

A ceramic electronic device includes: a multilayer chip having a structure in which each of dielectric layers and each of internal electrode layers are alternately stacked; and external electrodes provided on end faces of the multilayer chip, wherein a main component of the external electrodes is a first metal, wherein the internal electrode layers include the first metal and a second metal of which a melting point is higher than that of the first metal, wherein a diffusion coefficient of the first metal with respect to the second metal is larger than that of the second metal with respect to the first metal, wherein a number of a cavity in a range of 10 numbers of the internal electrode layers that are next to each other and are connected to a same external electrode of the first external electrode and the second external electrode is 1 or less.

Ceramic electronic device, circuit substrate and manufacturing method of ceramic electronic device

A multilayer ceramic capacitor includes an element body of roughly rectangular solid shape which is constituted by dielectric layers alternately stacked with internal electrode layers having different polarities, with a pair of cover layers formed on it to cover the top and bottom faces in the direction of lamination of the foregoing, and which has a pair of principal faces, a pair of end faces, and a pair of side faces, wherein external electrodes are formed on the pair of end faces and at least one of the pair of principal faces of the element body, and Tt representing the thickness of the external electrode and Tc representing the thickness of the cover layer satisfy the relationship of 1/30&#x2264;Tt/Tc&#x2264;4/5, and the thickness of the cover layers, or Tc, is 10 &#x3bc;m or more but 30 &#x3bc;m or less.

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Takasaki, Japan

Kotaro Mizuno