Nippon Telegraph and Telephone Public Corporation

Oki Electric Industry Co., Ltd.

Nippon Electric Co., Ltd.

Nec Corporation

Kabushiki Kaisha Daini

Kotaro Kato

Haruo Mori

Jun Ueda

Kazuo Hagimura

Hiroshi Tanabe

Yasuo Ohno

Yoshihito Amemiya

Yutaka Ohta

Masaharu Hata

Tetsuma Sakurai

Hirokazu Tsukada

Goro Oshima

Makoto Morimoto

Haruki Takai

An error correction code data communication system scrambles and descrambles both non-coded data and coded data by using substantially the same code process at the opposite ends of a transmission path. The frequency of the occurrence of an error correction pulse in a decoder is monitored to set up synchronization for descrambling. The transmitter includes an encoder for adding a correction code to a data signal to be transmitted, and a scrambler for randomizing the data signal. The receiver includes a descrambler for descrambling the data signal which was randomized by the scrambler, and a decoder for correcting a code error responsive to the error correction code. The scrambler modulo 2 adds an output of a random signal generator to both an input data signal and an output data signal. The descrambler modulo 2 adds an output of a second random signal generator to both an input data signal and an output data signal.

Digital communication system including an error correcting

The semiconductor device comprises a semiconductor substrate, a plurality of spaced active elements, for example, of a planer type formed on one surface of the substrate, and a supporting plate bonded to the opposite surface of the substrate. A groove is cut through the substrate to reach the supporting plate for isolating the active elements.

High voltage integrated semiconductor devices using a thermoplastic

A PNPN semiconductor switch including an N type semiconductor substrate, spaced apart first and second P type diffused regions formed on a surface of an N type substrate, spaced apart first and second N type diffused regions formed in the second P type diffused region, a first gate insulating layer formed on the surface of the second P type diffused region between the first and second N type diffused regions to cover portions thereof, a first gate electrode formed on the first gate insulating layer between the first and second N type diffused regions, a resistance region disposed on the first gate insulating layer, one end of the resistance region on the side opposite to the first gate electrode, a second gate insulating layer overlying the first gate electrode and the resistance region, a semiinsulating layer formed on the surface of the substrate except over the first and second P type diffused regions, an insulating layer overlying the semiinsulating layer, a P gate electrode electrically connected to the second P type diffused region and the second N type diffused region, a second gate electrode formed on the second gate insulating layer at a portion above the first gate electrode, a cathode electrode connected to the first N type diffused region, an anode electrode connected to the first P type diffused region and the second gate electrode and a high resistance region formed immediately beneath the first gate insulating layer and between the first and second N type diffused regions.

PNPN Light sensitive semiconductor switch with phototransistor connected

The semiconductor device is provided with semiconductor elements having the complementary characteristics and high breakdown strength. These semiconductor elements are formed in N and P islands respectively each having an inverted frustum shape. Surfaces of the frustum are inclined by an angle determined by semiconductor crystal structure. Side and bottom surfaces of the islands are formed adjacent to an insulating layer and both islands are supported part from the polycrystalline semiconductor layer. All side and bottom surfaces of the islands adjacent the insulating layer are made of high impurity substance of the same type as respective islands.

Method of manufacturing semiconductor device provided with complementary

A clock recovery circuit includes an oscillator having a frequency which is substantially equal to the clock frequency of bursts which are transmitted from a plurality of stations. A phase difference detector circuit responds to phase differences between clock signals extracted from each of the bursts and from the output from the oscillator. An averaging circuit averages the detected phase differences over an interval which is designated by a first control signal. A memory circuit stores the averaged phase difference in response to a second control signal and reads out the stored phase differences in response to a third control signal. A control circuit generates the first to third control signals in response to the output from the oscillator. A phase shift circuit shifts the phase of the output from the oscillator, based on the phase difference read out from the memory circuit. This generates and recovers the original clock pulse signal. The clock of the first burst corresponding to the stored phase difference is used as the clock for a second burst from the same station which transmits the first burst.

Clock recovery circuit for burst communications systems

A circuit for preventing a dV/dt erroneous operation of a PNPN semiconductor switch is replaced by a capacitance on the surface of a semiconductor substrate, a high resistance gate electrode. In other words, such a circuit is formed on the surface of the substrate by a slight modification of the basic design without decreasing the chip area and without isolating component elements.

PNPN Semiconductor switches

Current having a density higher than a critical value is passed through a polycrystalline resistor doped with impurities at a concentration higher than a critical value to decreasingly correct the initial value of the resistance, thereby trimming the resistance value of the resistor. When the resistor is used in a semiconductor integrated circuit, the current is passed through the existing (not additional) terminals of the integrated circuit.

Trimming method for resistance value of polycrystalline silicon

A clock signal reproducing network for PCM signal reception is capable of reproducing a clock signal even if the clock component is absent in the input digital signal for a prolonged period of time. The network includes a clock signal component extracting circuit and a bandpass filter for extracting and band-limiting the clock signal component in a received digital signal. An envelope detection circuit and a level decision circuit are connected to receive the output of the bandpass filter to provide a control signal to an output switching circuit. When the amplitude of the envelope of the filter output is high, the output of the bandpass filter is used directly as a reproduced clock signal. When the amplitude of the envelope is low, the clock signal obtained immediately before the filter amplitude becomes small is derived repeatedly from a delay circuit as a substituted clock signal.

Clock signal reproducing network for PCM signal reception

A quartz crystal timepiece incorporating a vibrator unit is disclosed. The vibrator unit is hermetically sealed in a case on which a condenser is fixed and the condenser compensates the oscillating frequency of said vibrator unit to a predetermined center frequency by suitably selecting the capacitance of the condenser after measuring the natural frequency of the vibrator unit. Then there is no need to adjust each vibrator unit to the predetermined center frequency during assembling process.

Growing community of inventors

Tokyo, Japan

Kotaro Kato