Matsushita Electric Industrial Co., Ltd.

Kosuke Yoshioka

Tokuzo Kiyohara

Makoto Hirai

Hideshi Nishida

Kozo Kimura

Hiroyuki Morishita

Toshiaki Tsuji

Tetsuji Mochida

Ryuji Matsuura

Hiroyuki Oka

Takaharu Tanaka

Yoshiyuki Wada

Kiyoshi Maenobu

Yukiharu Ieda

The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processoroutputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder

Image decoding apparatus, recording medium which computer can read from, and program which computer can read

A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

Transcoder

A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

Media processing apparatus which operates at high efficiency

In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

Apparatus, method, and computer program for resource request arbitration

The speed of decoding processing for variable-length coded image data is improved. The image processor includes a variable-length decoding unit for variable-length decoding input data and outputting a pair of the run length of zero coefficients and a non-zero coefficient; an inverse quantization unit for subjecting the non-zero coefficient to inverse quantization and obtaining inverse quantized data to be output; an address setting unit for carrying out inverse scanning, obtaining an address for storing the inverse quantized data on the basis of the run length of zero coefficients and specifying the address in the data storage unit; a write information storage unit for setting a write flag in an address thereof corresponding to the specified address; and a data reading unit for reading data from the data storage unit, and on the basis of information stored in the write information storage unit, directly outputting data from the address specified by the address setting unit while substituting a predetermined value for data from an address other than the specified address to output the substituted value.

Image processor and image processing method

A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit for decoding compressed video data to produce frame data, frame memory for storing the frame data, a filtering unit for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory for storing the reduced image outputted from filtering unit , and a control unit for controlling filtering unit based on a decoding state of the video data by decoding unit and a filtering state of the frame data by filtering unit , so that overrun and underrun do not occur in filtering unit

Pixel calculating device

A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group , and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

The counter is set with an initial value of &ldquo;1&rdquo; and is a counter with a maximum value of &ldquo;4&rdquo;. This counter increments the count value held by the flip-flop in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit to control the execution of instructions, with the counting by the counter being performed once for each instruction execution performed by the instruction decode control unit . The comparator compares the count value counted by the counter with the maximum value &ldquo;4&rdquo;, and when the values match, sets the task switching signal chg_task_ex at a &ldquo;High&rdquo; value, so that the processing switches to the execution of the next task.

Processor capable of efficiently executing many asynchronous event tasks

A first bit string extracting unit extracts a first bit string. A first bit length judging unit detects a first codeword from the first bit string. A first decoding unit generates a first run-level pair from the first codeword. A second bit string extracting unit extracts a second bit string. A second bit length judging unit detects a second codeword from the second bit string. A second decoding unit generates a second run-level pair from the second codeword. A first inverse quantizing unit inverse quantizes the first level to obtain a DCT coefficient. A second inverse quantizing unit inverse quantizes the second level to obtain a DCT coefficient. A second buffer controller writes the DCT coefficients and their first buffer addresses into a second buffer. A first buffer controller reads the DCT coefficients and the first buffer addresses from the second buffer and writes the DCT coefficients into a first buffer at the respective first buffer addresses.

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Daito, Japan

Kosuke Yoshioka