Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Kosuke Yanagidaira

Chikaaki Kodama

Shouichi Ozaki

Kensuke Yamamoto

Mario Sako

Hiroshi Tsubouchi

Takuyo Kodama

Yoshikazu Harada

Takeshi Hioka

Yoko Deguchi

Yuko Utsunomiya

Hayato Konno

Hiroe Kami

Toshihiro Suzuki

Yoshihiko Kamata

Koichi Fukuda

Tsukasa Kobayashi

Takahiko Hara

Jun Nakai

Kazuhide Yoneya

Koji Hashimoto

Takuya Futatsuyama

Toshiya Kotani

Naoya Tokiwa

Kazuyuki Masukawa

Kenro Kubota

Fumiya Watanabe

Hidefumi Mukai

Yuki Shimizu

Tadashi Yasufuku

Tomofumi Fujimura

Jiyun Nakai

According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.

Semiconductor device

A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Manufacturing method of a semiconductor device and method for creating a layout thereof

A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.

Semiconductor memory device with first and second sense amplifiers

A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1verification operation is ended after a kverification operation is ended in the nwrite loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nwrite loop is supplied to the word line before start of the k+1verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1verification operation is shorter than a time from start of the first verification operation to end of the kverification operation in the nwrite loop.

Semiconductor storage device

According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.

Semiconductor memory

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.

Semiconductor device and memory system

A semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.

A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through the second and third transistors.

A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

Growing community of inventors

Fujisawa, Japan

Kosuke Yanagidaira