Ablic Inc.

Sii Semiconductor Corporation

Seiko Instruments Inc

Seiko Instrumentals Inc.

Kosuke Takada

Michiyasu Deguchi

Hiroyuki Masuko

Masayuki Uno

Masakazu Sugiura

Atsushi Igarashi

Akihiro Kawano

Nao Otsuka

Tetsuya Makino

Provided is a constant voltage circuit with which a variation of an output voltage in response to a sudden change of a power supply voltage is small. The constant voltage circuit includes: an ED-type reference voltage circuit including at least two depletion mode transistors and an enhancement mode transistor which are connected in series; a depletion mode transistor connected in series between the power supply terminal and the ED-type reference voltage circuit; a first output terminal or a second output terminal; and a power supply variation suppression circuit which is connected between a connection point and the ground terminal and which suppresses a variation of the power supply voltage. The power supply variation suppression circuit includes a detection circuit which detects whether there is a variation of the power supply voltage, and a pass transistor which is connected in parallel to the detection circuit.

Constant voltage circuit

A voltage follower circuit includes a first MOS transistor which has a source connected to an input port, a second MOS transistor which has a source connected to an output port and has a gate and a drain connected to a gate of the first MOS transistor, a first constant current source connected between a drain of the first MOS transistor and a second power supply terminal, a second constant current source connected between the drain of the second MOS transistor and the second power supply terminal, and a depletion type third MOS transistor which has a gate connected to the drain of the first MOS transistor, has a drain connected to a first power supply terminal, and has a source connected to the output port.

Voltage follower circuit

A constant voltage circuit includes a depletion transistor having a drain, a gate, and a source, the drain connected to a first power supply terminal, and the gate connected to the source, a voltage division circuit connected between the first power supply terminal and an output terminal, a first enhancement transistor having a drain connected to the source of the depletion transistor, a source connected to the output terminal, and a gate connected to an output terminal of the voltage division circuit, a second enhancement transistor having a source connected to the first power supply terminal, a drain connected to the output terminal, and a gate connected to the drain of the first enhancement transistor, and a pull-down element having one end connected to the output terminal and the other end connected to a second power supply terminal.

A switching regulator has an error amplifier supplying an error current, a phase compensation portion generating an error voltage, a clamper clamping the error voltage, a PFM detector supplying a comparison result signal of a first level or a comparison result signal of a second level based on the error current, an oscillator supplying a clock signal in response to the comparison result signal at the second level and fixing the clock signal in response to the comparison result signal at the first level, and a PWM converter turning on/off a switching element with a desired pulse width based on the error voltage and the output from the oscillator.

Switching regulator including PFM detector

Provided is an switching regulator including: an error amplification circuit configured to output a first error voltage based on an output voltage and a first reference voltage; a PFM comparison circuit configured to compare the first error voltage with a second reference voltage to output a comparison result signal; an oscillation circuit configured to output a clock signal, and to stop output of the clock signal depending on the comparison result signal; a frequency characteristics separation circuit to which the first error voltage is provided, and from which a second error voltage is supplied; a phase compensation circuit connected to the frequency characteristics separation circuit; and a PWM conversion circuit configured to turn the switching element on and off at a desired pulse width, based on the second error voltage and on the output from the oscillation circuit.

Switching regulator with a frequency characteristics separation circuit and a phase compensation circuit

A level shift circuit includes two resistors by which logic is fixed when two input terminals become low level, and a logic circuit and transistors which set the logic of an output terminal to a desired value according to the fixation of the logic.

Level shift circuit

A switching regulator includes a switching element, a first error amplification circuit amplifying a difference between a voltage based on an output voltage and a first reference voltage and providing a first error voltage, a clamp circuit generating a second error voltage at an output node based on the first error voltage and a second reference voltage, a PFM comparison circuit comparing the second error voltage and the second reference voltage to output a comparison result, an oscillation circuit providing and stopping a clock signal according to the comparison result, and a PWM conversion circuit turning on/off the switching element based on the second error voltage and the output of the oscillation circuit. The clamp circuit clamps a lower limit value of the second error voltage to a voltage obtained by subtracting a prescribed voltage from the second reference voltage.

Switching regulator including a clamp circuit

A switching regulator includes: an error amplification circuit configured to amplify a difference between a voltage based on the output voltage and a first reference voltage to output an error voltage; a PFM comparison circuit configured to compare the error voltage with a second reference voltage to output a comparison result signal at a first level or a second level, an offset being given to the error voltage for a given period in response to a change of the comparison result signal from the second level to the first level; an oscillation circuit configured to output a clock signal of a given frequency according to the first level of the comparison result signal, and to stop outputting the clock signal according to the second level of the comparison result signal; and a PWM conversion circuit configured to turn the switching element on at a prescribed pulse width.

Switching regulator including an offset enabled comparison circuit

A switching regulator includes a clamp circuit which clamps the output voltage of the error amplifier to the clamp voltage when an output voltage of an error amplifier is higher than a clamp voltage, a constant voltage generation circuit having one end connected to an output terminal of the error amplifier, and a phase compensation capacitor having one end connected to the other end of the constant voltage generation circuit, and the other end connected to a ground terminal. When the clamp circuit clamps the output voltage of the error amplifier, the constant voltage generation circuit lowers the voltage at one end of the phase compensation capacitor by a prescribed voltage. When the clamped state of the output voltage of the error amplifier is released, the constant voltage generation circuit lowers the voltage of the output terminal of the error amplifier from the clamp voltage by the prescribed voltage.

Switching regulator

Provided are a switching regulator and a voltage-current conversion circuit configured to shorten a start-up period. The voltage-current conversion circuit includes: a first MOS transistor of a first conductivity type including a gate and a drain connected in common, and a source connected to a first power supply terminal; a first resistor connected between the drain of the first MOS transistor and a second power supply terminal; and a correction current generation unit including a second resistor, and configured to generate, as a correction current, through use of the second resistor, a current corresponding to a current generated when a voltage corresponding to an absolute value of a gate-source voltage of the first MOS transistor is applied to the first resistor. The voltage-current conversion circuit is configured to add the correction current to a current flowing through the first resistor, to thereby generate the conversion current.

Voltage-current conversion circuit and switching regulator including the same

The output circuit includes: a control voltage generating circuit configured to generate a control voltage; a first MOS transistor having a gate for receiving the control voltage; a second MOS transistor having a gate to which a first input signal is input; a third MOS transistor having a gate to which a second input signal is input; and a fourth MOS transistor which has a gate connected to a source of the first MOS transistor, and a drain connected to an output terminal, and is configured to be driven with the first input signal and the second input signal to output an output signal to the output terminal. The control voltage generating circuit is configured to absorb fluctuations in control voltage, which are caused due to changes in first input signal and second input signal, to thereby maintain the control voltage at a predetermined voltage.

Output circuit

To provide an oscillation circuit device capable of when detecting an input reference signal and making a transition from a self-running state to a PLL operation, suppressing a fluctuation in the frequency of an output signal CLK to thereby obtain a smoothly-synchronized and stable output signal CLK. There is provided an oscillation circuit device which is adapted to configure a negative feedback circuit by a V/I conversion element to which one end of a filter circuit is connected, and a buffer circuit in a self-running state, and has a configuration which enables a capacitance in the filter circuit to be charged rapidly in such a manner that an output signal CLK can be started from a frequency equal to that in the self-running state immediately after a transition to a PLL operation.

Oscillation circuit device

Provided is a voltage regulator capable of suppressing fluctuation in a limited current. The voltage regulator includes: a first differential amplifier circuit configured to compare a voltage based on an output voltage and a reference voltage to each other, to thereby output a first voltage; a second differential amplifier circuit configured to compare the first voltage and a second voltage to each other, to thereby output a third voltage; a first transistor configured to receive the third voltage at a gate thereof such that the output voltage is generated at a drain thereof; a second transistor, which includes a gate connected in common to the gate of the first transistor and has a predetermined size ratio to the first transistor; and a voltage generating unit, which includes one end connected to a drain of the second transistor and is configured to generate the second voltage at the one end.

Voltage regulator

Provided is a level shift circuit capable of avoiding breakdown due to level shift operation. The level shift circuit includes: a floating power supply having one end connected to an output terminal; a circuit configured to receive a voltage of the floating power supply, a voltage of a low level power supply and first and second pulse signals from a pulse generating circuit, thereof to output first and second signals; and a logic circuit configured to receive first and second signals, thereby converting a signal that is input to the pulse generating circuit into a signal that fluctuates between a voltage at the one end of the floating power supply and a voltage at the other end thereof to output the converted signal.

Provided is a reference voltage circuit capable of adjusting an arbitrary output voltage to have arbitrary temperature characteristics. The reference voltage circuit includes: a reference current generating circuit configured to convert a difference between forward voltages of a plurality of PN junction elements into current to generate a first current; a current generating circuit configured to use the first current generated by the reference current generating circuit to generate a second current; and a voltage generating circuit including a first resistive element and a second resistive element, the first resistive element being configured to generate a first voltage having positive temperature characteristics when the first current flows through the first resistive element, the second resistive element being configured to generate a second voltage having negative temperature characteristics when the first current and the second current flow through the second resistive element. The reference voltage circuit outputs a reference voltage obtained by adding the first voltage to the second voltage.

Growing community of inventors

Chiba, Japan

Kosuke Takada