Fujitsu Corporation

Kosuke Suzuki

Hirotaka Tamura

Kohta Nakashima

Jun Kato

An information processing apparatus configured to be coupled via a communication line to a plurality of nodes each having a storage device, the information processing apparatus includes a memory; and a processor coupled to the memory and configured to determine, from among a plurality of nodes, a location where a virtual machine is to be placed, determine that a location where management information on data to be processed, the data to be accessed from the virtual machine, is to be stored is, among the plurality of nodes, a node that is identical to the location of the virtual machine, and store the management information in the determined node.

Information processing apparatus, information processing method for reducing network traffic, and storage medium

A specifying unit specifies one or more dividing positions in input data. A common region compressing unit specifies compression positions in the input data corresponding to positions at which sizes from two ends of compressed, data are equal to or larger than a predetermined, size and corresponding to positions which sandwich adjacently-positioned dividing positions and of which a size therebetween is equal to or larger than the predetermined size and compresses former compression data that are arranged in a row in the input data on either side of each of the dividing positions and that are interposed between the compression positions. An individual region compressing unit compresses latter compression data that are separated fay any of the pieces of former compression data in the input data, based on the former compression data positioned adjacent to the piece of latter compression data and the piece of latter compression data.

Information processing apparatus, data compressing method, and computer-readable recording medium

An information processing device includes a memory, and a plurality of processor cores that access the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes. When a polling process for repeatedly determining whether reception data for input/output processing is received is underway in one of the plurality of processor cores, the plurality of processor cores respectively executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, the plurality of processor cores respectively executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.

Information processing device, information processing method, and program

A signal transmission circuit includes a driver circuit that includes complementary inverters, each of the complementary inverters including a plurality of transistor switches, each of the plurality of transistor switches including a pair of transistors, one of the pair of transistors operating in a saturation region and another of the pair of transistors operating in a triode region to cause a certain impedance, and that drives each of the plurality of transistor switches in accordance with complementary signals so as to output complementary voltages to a transmission line; and first voltage sources that supply operating voltages to the driver circuit so as to adjust amplitudes of the complementary voltages output from the driver circuit to the transmission line.

Signal transmission circuit, signal transmission system, and signal transmission method

A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock.

Clock recovery circuit and clock and data recovery circuit

A transmission circuit is formed such that plural driver units of each driver circuit are connected together in parallel. A code setting section detects a voltage Vms output from a replica circuit corresponding to a driver unit of a driver circuit, and detects a voltage Vmo output from a replica circuit corresponding to one driver unit of the driver circuit, and based on a ratio of the voltages Vms, Vmo, sets operation numbers Na to Nd of driver units for each of the driver circuits such that the output resistance value of each of the driver circuits becomes pre-set output resistance values Roa to Rod. The driver circuit has a number of driver units according to the operation number connected together in parallel and operating.

Growing community of inventors

Ota, Japan

Kosuke Suzuki