Shindengen Electric Manufacturing Company Limited

Kosuke Ohshima

Mizue Kitada

Shinji Kunori

Hiroaki Shishido

Toru Kurosaki

Masato Mikawa

Masahiro Kuriyama

A semiconductor device having high withstand strength against destruction. The semiconductor deviceincludes guard buried regionsof second conductivity type concentrically provided on a resistance layerof first conductivity type and base diffusion regionsare provided inside of the guard buried regionand base buried regionsof the second conductivity type are provided on the bottom surface of the base diffusion regions. A distance between adjacent base buried regionsat the bottom of the same base diffusion regionis Wm, a distance between adjacent base buried regionsat the bottom of the different base diffusion regionsis Wm, and a distance between the guard buried regionsis W. A ratio of an impurity quantity Qof the first conductivity type and an impurity quantity Qof the second conductivity type included inside the widthwise center of the innermost guard buried regionis 0.90&#x3c;Q/Qwhen Wm&#x3c;W&#x3c;Wm. When W&#x3c;Wm&#x3c;Wm, the ratio is Q/Q&#x3c;0.92 and when Wm&#x3c;Wm&#x3c;W, the ratio is 1.10&#x3c;Q/Q.

Semiconductor device

A semiconductor device having high withstand voltage is provided. An active grooveincludes a long and narrow main groove partand a sub groove partconnected to a longitudinal side surface of the main groove part, and a buried regionof a second conductivity type whose height is lower than the bottom surface of the base diffusion regionof the second conductivity type is provided on the bottom surface of the main groove part. An active groove filling regionof the second conductivity type in contact with the base diffusion regionis provided in the sub groove part. The buried regionis contacted to the base diffusion regionthrough the active groove filling region. Since one gate grooveis formed by the part above the buried regionin one active groove, the gate electrode plugsare not separated, which allows the electrode pattern to be simplified.

Semiconductor device and method for manufacturing thereof

A semiconductor device having high ruggedness is provided. The distance Wmbetween buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wmbetween buried regions positioned at the bottom of the same base diffusion region (Wm&#x3e;Wm). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.

A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

An active groove filled regionis kept at a portion of an active grooveconnecting to an embedded regionpositioned below a gate groove. The active groove filled regionconnects to a source electrode filmso as to have the same electric potential as a source region. When a reverse bias is applied between a base regionand a conductive layer, a reverse bias is also applied between the embedded regionand the conductive layer; and therefore, depletion layers spread out together and a withstanding voltage is increased.

Trench-type power MOSFET with embedded region at the bottom of the gate and increased breakdown voltage

A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.

A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.

Growing community of inventors

Saitama, Japan

Kosuke Ohshima